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### Folder structure
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- **FMC-masterFIP core**: masterfip-gw/rtl/
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- **General-cores**: masterfip-gw/ip\_cores/
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- **Simulation testbench** : masterfip-gw/sim
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- **ISE project**: masterfip-gw/syn/
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- **SPEC carrier top level**: masterfip-gw/top/spec
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- **rtl**: FMC-masterFIP core
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- **ip\_cores**: general-cores
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- **sim**: simulation testbench
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- **syn**: Xilinx ISE project
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- **top/spec**: SPEC carrier top level
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### Git sub-modules
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