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... | @@ -39,12 +39,12 @@ mezzanine |
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### Folder structure
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### Folder structure
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- sources: hdl/rtl/
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- Fmc worldFIP core sources: masterfip-gw/rtl/
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- required hdl cores: hdl/ip\_cores/
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- Required hdl cores: masterfip-gw/ip\_cores/
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- top levels: hdl/top/
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- VHDL Testbench : masterfip-gw/sim
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- ISE project: hdl/syn/
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- Mock-turtle SW sources for simulation: masterfip-gw/sw
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- testbench : hdl/sim
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- ISE project: masterfip-gw/syn/
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- gateware documentation: doc/ (%(red)coming soon)
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- SPEC carrier top levels: masterfip-gw/top/spec
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-----
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-----
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