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legacy-vme64x-core
Commits
3e64397d
Commit
3e64397d
authored
Dec 10, 2013
by
Cesar Prados
Browse files
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Plain Diff
msi:interrupts: add dtack_eo to bus struct
parent
e6b0e63d
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Showing
5 changed files
with
75 additions
and
43 deletions
+75
-43
VME_Buffer_pack.vhd
hdl/VME_Buffer_pack.vhd
+26
-4
VME_IRQ_Controller.vhd
hdl/VME_IRQ_Controller.vhd
+16
-7
VME_bus.vhd
hdl/VME_bus.vhd
+16
-16
xVME64xCore_Top.vhd
hdl/xVME64xCore_Top.vhd
+7
-8
xvme64x_pack.vhd
hdl/xvme64x_pack.vhd
+10
-8
No files found.
hdl/VME_Buffer_pack.vhd
View file @
3e64397d
...
...
@@ -91,6 +91,7 @@ package body VME_Buffer_pack is
vme_buff
.
s_dataDir
:
=
VME2FPGA
;
vme_buff
.
s_buffer_eo
:
=
ADDR_BUFF
;
vme_buff
.
s_clk
:
=
'1'
;
vme_buff
.
s_dtack_oe
:
=
'0'
;
when
DECODE_ACCESS
=>
...
...
@@ -98,6 +99,7 @@ package body VME_Buffer_pack is
vme_buff
.
s_dataDir
:
=
VME2FPGA
;
vme_buff
.
s_buffer_eo
:
=
ADDR_BUFF
;
vme_buff
.
s_clk
:
=
'0'
;
vme_buff
.
s_dtack_oe
:
=
'0'
;
when
WAIT_FOR_DS
|
LATCH_DS1
|
LATCH_DS2
|
LATCH_DS3
|
LATCH_DS4
=>
...
...
@@ -117,6 +119,7 @@ package body VME_Buffer_pack is
end
if
;
vme_buff
.
s_clk
:
=
'0'
;
vme_buff
.
s_dtack_oe
:
=
'1'
;
when
CHECK_TRANSFER_TYPE
|
MEMORY_REQ
=>
...
...
@@ -135,6 +138,7 @@ package body VME_Buffer_pack is
end
if
;
vme_buff
.
s_clk
:
=
'0'
;
vme_buff
.
s_dtack_oe
:
=
'1'
;
when
DATA_TO_BUS
|
DTACK_LOW
|
DECIDE_NEXT_CYCLE
=>
...
...
@@ -153,6 +157,7 @@ package body VME_Buffer_pack is
end
if
;
vme_buff
.
s_clk
:
=
'1'
;
vme_buff
.
s_dtack_oe
:
=
'1'
;
when
INCREMENT_ADDR
|
SET_DATA_PHASE
=>
...
...
@@ -171,13 +176,30 @@ package body VME_Buffer_pack is
end
if
;
vme_buff
.
s_clk
:
=
'0'
;
vme_buff
.
s_dtack_oe
:
=
'1'
;
when
DATA_OUT
=>
vme_buff
.
s_addrDir
:
=
VME2FPGA
;
vme_buff
.
s_dataDir
:
=
FPGA2VME
;
vme_buff
.
s_buffer_eo
:
=
DATA_BUFF
;
vme_buff
.
s_clk
:
=
'0'
;
vme_buff
.
s_dtack_oe
:
=
'1'
;
when
DTACK
=>
vme_buff
.
s_addrDir
:
=
VME2FPGA
;
vme_buff
.
s_dataDir
:
=
FPGA2VME
;
vme_buff
.
s_buffer_eo
:
=
DATA_BUFF
;
vme_buff
.
s_clk
:
=
'1'
;
vme_buff
.
s_dtack_oe
:
=
'1'
;
when
others
=>
vme_buff
.
s_addrDir
:
=
VME2FPGA
;
vme_buff
.
s_dataDir
:
=
VME2FPGA
;
vme_buff
.
s_buffer_eo
:
=
ADDR_BUFF
;
vme_buff
.
s_clk
:
=
'0'
;
vme_buff
.
s_dtack_oe
:
=
'0'
;
end
case
;
return
vme_buff
;
...
...
hdl/VME_IRQ_Controller.vhd
View file @
3e64397d
...
...
@@ -102,6 +102,8 @@ library IEEE;
use
IEEE
.
STD_LOGIC_1164
.
ALL
;
use
IEEE
.
numeric_std
.
all
;
use
work
.
xvme64x_pack
.
all
;
use
work
.
VME_Buffer_pack
.
all
;
--===========================================================================
-- Entity declaration
--===========================================================================
...
...
@@ -118,10 +120,11 @@ entity VME_IRQ_Controller is
INT_Vector_i
:
in
std_logic_vector
(
7
downto
0
);
INT_Req_i
:
in
std_logic
;
VME_IRQ_n_o
:
out
std_logic_vector
(
6
downto
0
);
VME_DATA_o
:
out
std_logic_vector
(
31
downto
0
);
VME_IACKOUT_n_o
:
out
std_logic
;
VME_DTACK_n_o
:
out
std_logic
;
VME_DTACK_OE_o
:
out
std_logic
;
VME_DATA_o
:
out
std_logic_vector
(
31
downto
0
)
;
------------------------------------------------------------------
-- VME_DTACK_OE_o : out std_logic
;
-- VME_DATA_DIR_o : out std_logic);
VME_BUFFER_o
:
out
t_VME_BUFFER
);
end
VME_IRQ_Controller
;
...
...
@@ -132,7 +135,8 @@ architecture Behavioral of VME_IRQ_Controller is
--input signals
signal
s_INT_Req_sample
:
std_logic
;
--output signals
signal
s_DTACK_OE_o
:
std_logic
;
--signal s_DTACK_OE_o : std_logic;
signal
s_buffer
:
t_VME_BUFFER
;
signal
s_enable
:
std_logic
;
signal
s_IRQ
:
std_logic_vector
(
6
downto
0
);
signal
s_Data
:
std_logic_vector
(
31
downto
0
);
...
...
@@ -193,7 +197,8 @@ begin
DTACKOEOutputSample
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
s_DTACK_OE_o
<=
s_FSM_IRQ
.
s_DTACK_OE
;
--s_DTACK_OE_o <= s_FSM_IRQ.s_DTACK_OE;
s_buffer
<=
s_FSM_IRQ
.
s_buffer
;
end
if
;
end
process
;
...
...
@@ -348,14 +353,16 @@ begin
when
DATA_OUT
=>
s_FSM_IRQ
<=
c_FSM_IRQ
;
--s_FSM_IRQ.s_DataDir <= '1';
--s_FSM_IRQ.s_DTACK_OE <= '1';
s_FSM_IRQ
.
s_buffer
<=
buffer_function
(
s_currs
,
'0'
,
'0'
);
s_FSM_IRQ
.
s_resetIRQ
<=
'0'
;
s_FSM_IRQ
.
s_DTACK_OE
<=
'1'
;
when
DTACK
=>
s_FSM_IRQ
<=
c_FSM_IRQ
;
--s_FSM_IRQ.s_DataDir <= '1';
--s_FSM_IRQ.s_DTACK_OE <= '1';
s_FSM_IRQ
.
s_buffer
<=
buffer_function
(
s_currs
,
'0'
,
'0'
);
s_FSM_IRQ
.
s_DTACK
<=
'0'
;
s_FSM_IRQ
.
s_DTACK_OE
<=
'1'
;
when
others
=>
null
;
end
case
;
...
...
@@ -420,7 +427,9 @@ begin
s_Data
<=
x"000000"
&
INT_Vector_i
;
s_enable
<=
(
not
s_INT_Req_sample
)
or
((
not
s_FSM_IRQ
.
s_DTACK
)
and
(
s_AS_RisingEdge
));
-- the INT_Vector is in the D0:D7 lines (byte3 in big endian order)
VME_DTACK_OE_o
<=
s_DTACK_OE_o
;
--VME_DTACK_OE_o <= s_DTACK_OE_o;
VME_BUFFER_o
<=
s_buffer
;
VME_IACKOUT_n_o
<=
s_FSM_IRQ
.
s_IACKOUT
;
end
Behavioral
;
--===========================================================================
...
...
hdl/VME_bus.vhd
View file @
3e64397d
...
...
@@ -99,7 +99,7 @@ entity VME_bus is
VME_DS_n_i
:
in
std_logic_vector
(
1
downto
0
);
VME_DS_ant_n_i
:
in
std_logic_vector
(
1
downto
0
);
VME_DTACK_n_o
:
out
std_logic
;
VME_DTACK_OE_o
:
out
std_logic
;
--
VME_DTACK_OE_o : out std_logic;
VME_BERR_o
:
out
std_logic
;
VME_ADDR_i
:
in
std_logic_vector
(
31
downto
1
);
VME_ADDR_o
:
out
std_logic_vector
(
31
downto
1
);
...
...
@@ -173,7 +173,7 @@ architecture RTL of VME_bus is
signal
s_LWORDinput
:
std_logic
;
-- External buffer signals
signal
s_dtackOE
:
std_logic
;
--
signal s_dtackOE : std_logic;
signal
s_buffer
:
t_VME_BUFFER
;
--signal s_dataBuf : t_VME_BUFFER;
--signal s_dataDir : std_logic;
...
...
@@ -345,7 +345,7 @@ begin
--VME_ADDR_BUFF_o <= s_addrBuf;
VME_BUFFER_o
<=
s_buffer
;
VME_DTACK_OE_o
<=
s_dtackOE
;
--
VME_DTACK_OE_o <= s_dtackOE;
-- VME DTACK:
VME_DTACK_n_o
<=
s_mainDTACK
;
...
...
@@ -480,7 +480,7 @@ with s_addressingType select
-------------------------------------MAIN FSM--------------------------------|
s_memReq
<=
s_FSM
.
s_memReq
;
s_decode
<=
s_FSM
.
s_decode
;
s_dtackOE
<=
s_FSM
.
s_dtackOE
;
--
s_dtackOE <= s_FSM.s_dtackOE;
s_mainDTACK
<=
s_FSM
.
s_mainDTACK
;
--s_dataBuf <= s_FMS.s_dataBuf;
--s_addrBuf <= s_FMS.s_addrBuf;
...
...
@@ -549,7 +549,7 @@ with s_addressingType select
when
WAIT_FOR_DS
=>
-- wait until DS /= "11"
s_FSM
<=
c_FSM_default
;
s_FSM
.
s_dtackOE
<=
'1'
;
--
s_FSM.s_dtackOE <= '1';
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM
.
s_buffer
<=
buffer_function
(
s_mainFSMstate
,
s_is_d64
,
VME_WRITE_n_i
);
s_FSM
.
s_DSlatch
<=
'1'
;
...
...
@@ -566,7 +566,7 @@ with s_addressingType select
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
s_FSM
<=
c_FSM_default
;
s_FSM
.
s_dtackOE
<=
'1'
;
--
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dataDir <= VME_WRITE_n_i;
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM
.
s_buffer
<=
buffer_function
(
s_mainFSMstate
,
s_is_d64
,
VME_WRITE_n_i
);
...
...
@@ -584,7 +584,7 @@ with s_addressingType select
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
s_FSM
<=
c_FSM_default
;
s_FSM
.
s_dtackOE
<=
'1'
;
--
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dataDir <= VME_WRITE_n_i;
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM
.
s_buffer
<=
buffer_function
(
s_mainFSMstate
,
s_is_d64
,
VME_WRITE_n_i
);
...
...
@@ -602,7 +602,7 @@ with s_addressingType select
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
s_FSM
<=
c_FSM_default
;
s_FSM
.
s_dtackOE
<=
'1'
;
--
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dataDir <= VME_WRITE_n_i;
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM
.
s_buffer
<=
buffer_function
(
s_mainFSMstate
,
s_is_d64
,
VME_WRITE_n_i
);
...
...
@@ -620,7 +620,7 @@ with s_addressingType select
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
s_FSM
<=
c_FSM_default
;
s_FSM
.
s_dtackOE
<=
'1'
;
--
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dataDir <= VME_WRITE_n_i;
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM
.
s_buffer
<=
buffer_function
(
s_mainFSMstate
,
s_is_d64
,
VME_WRITE_n_i
);
...
...
@@ -634,7 +634,7 @@ with s_addressingType select
when
CHECK_TRANSFER_TYPE
=>
s_FSM
<=
c_FSM_default
;
s_FSM
.
s_dtackOE
<=
'1'
;
--
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dataDir <= VME_WRITE_n_i;
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
...
...
@@ -656,7 +656,7 @@ with s_addressingType select
-- To request the memory CR/CSR or WB memory it is sufficient to
-- generate a pulse on s_memReq signal
s_FSM
<=
c_FSM_default
;
s_FSM
.
s_dtackOE
<=
'1'
;
--
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dataDir <= VME_WRITE_n_i;
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM
.
s_buffer
<=
buffer_function
(
s_mainFSMstate
,
s_is_d64
,
VME_WRITE_n_i
);
...
...
@@ -678,7 +678,7 @@ with s_addressingType select
when
DATA_TO_BUS
=>
s_FSM
<=
c_FSM_default
;
s_FSM
.
s_dtackOE
<=
'1'
;
--
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dataDir <= VME_WRITE_n_i;
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM
.
s_buffer
<=
buffer_function
(
s_mainFSMstate
,
s_is_d64
,
VME_WRITE_n_i
);
...
...
@@ -691,7 +691,7 @@ with s_addressingType select
when
DTACK_LOW
=>
s_FSM
<=
c_FSM_default
;
s_FSM
.
s_dtackOE
<=
'1'
;
--
s_FSM.s_dtackOE <= '1';
--s_FSM.s_dataDir <= VME_WRITE_n_i;
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM
.
s_buffer
<=
buffer_function
(
s_mainFSMstate
,
s_is_d64
,
VME_WRITE_n_i
);
...
...
@@ -719,7 +719,7 @@ with s_addressingType select
when
DECIDE_NEXT_CYCLE
=>
s_FSM
<=
c_FSM_default
;
s_FSM
.
s_dtackOE
<=
'1'
;
--
s_FSM.s_dtackOE <= '1';
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM
.
s_buffer
<=
buffer_function
(
s_mainFSMstate
,
s_is_d64
,
VME_WRITE_n_i
);
...
...
@@ -739,7 +739,7 @@ with s_addressingType select
when
INCREMENT_ADDR
=>
s_FSM
<=
c_FSM_default
;
s_FSM
.
s_dtackOE
<=
'1'
;
--
s_FSM.s_dtackOE <= '1';
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM
.
s_buffer
<=
buffer_function
(
s_mainFSMstate
,
s_is_d64
,
VME_WRITE_n_i
);
...
...
@@ -750,7 +750,7 @@ with s_addressingType select
when
SET_DATA_PHASE
=>
s_FSM
<=
c_FSM_default
;
s_FSM
.
s_dtackOE
<=
'1'
;
--
s_FSM.s_dtackOE <= '1';
--s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM
.
s_buffer
<=
buffer_function
(
s_mainFSMstate
,
s_is_d64
,
VME_WRITE_n_i
);
s_FSM
.
s_dataPhase
<=
'1'
;
...
...
hdl/xVME64xCore_Top.vhd
View file @
3e64397d
...
...
@@ -92,7 +92,7 @@
VME_IACKOUT_n_o
:
out
std_logic
;
-- VME buffers
VME_DTACK_OE_o
:
out
std_logic
;
--
VME_DTACK_OE_o : out std_logic;
--VME_DATA_BUFF_o : out t_VME_BUFFER;
--VME_ADDR_BUFF_o : out t_VME_BUFFER;
...
...
@@ -143,8 +143,8 @@
signal
s_fifo
:
std_logic
;
signal
s_VME_DTACK_VMEbus
:
std_logic
;
signal
s_VME_DTACK_IRQ
:
std_logic
;
signal
s_VME_DTACK_OE_VMEbus
:
std_logic
;
signal
s_VME_DTACK_OE_IRQ
:
std_logic
;
--
signal s_VME_DTACK_OE_VMEbus : std_logic;
--
signal s_VME_DTACK_OE_IRQ : std_logic;
--signal s_VME_DATA_DIR_VMEbus : std_logic;
--signal s_VME_DATA_BUFF_VMEbus : t_VME_BUFFER;
--signal s_VME_DATA_DIR_IRQ : std_logic;
...
...
@@ -285,7 +285,7 @@ begin
VME_DS_n_i
=>
VME_DS_n_oversampled
,
VME_DS_ant_n_i
=>
VME_DS_n_oversampled_1
,
VME_DTACK_n_o
=>
s_VME_DTACK_VMEbus
,
VME_DTACK_OE_o
=>
s_VME_DTACK_OE_VMEbus
,
--
VME_DTACK_OE_o => s_VME_DTACK_OE_VMEbus,
VME_BERR_o
=>
VME_BERR_o
,
VME_ADDR_i
=>
VME_ADDR_i
,
VME_ADDR_o
=>
VME_ADDR_o
,
...
...
@@ -357,8 +357,8 @@ begin
s_VME_DATA_IRQ
;
VME_DTACK_n_o
<=
s_VME_DTACK_VMEbus
when
VME_IACK_n_oversampled
=
'1'
else
s_VME_DTACK_IRQ
;
VME_DTACK_OE_o
<=
s_VME_DTACK_OE_VMEbus
when
VME_IACK_n_oversampled
=
'1'
else
s_VME_DTACK_OE_IRQ
;
--
VME_DTACK_OE_o <= s_VME_DTACK_OE_VMEbus when VME_IACK_n_oversampled ='1' else
--
s_VME_DTACK_OE_IRQ;
--VME_DATA_DIR_o <= s_VME_DATA_DIR_VMEbus when VME_IACK_n_oversampled ='1' else
-- s_VME_DATA_DIR_IRQ;
--VME_DATA_BUFF_o <= s_VME_DATA_BUFF_VMEbus when VME_IACK_n_oversampled ='1' else
...
...
@@ -382,10 +382,9 @@ begin
VME_IRQ_n_o
=>
s_VME_IRQ_n_o
,
VME_IACKOUT_n_o
=>
VME_IACKOUT_n_o
,
VME_DTACK_n_o
=>
s_VME_DTACK_IRQ
,
VME_DTACK_OE_o
=>
s_VME_DTACK_OE_IRQ
,
VME_DATA_o
=>
s_VME_DATA_IRQ
,
--VME_DTACK_OE_o => s_VME_DTACK_OE_IRQ,
--VME_DATA_DIR_o => s_VME_DATA_DIR_IRQ
--VME_DATA_BUFF_o => s_VME_DATA_BUFF_IRQ
VME_BUFFER_o
=>
s_VME_BUFFER_IRQ
);
...
...
hdl/xvme64x_pack.vhd
View file @
3e64397d
...
...
@@ -49,15 +49,16 @@ package xvme64x_pack is
s_clk
:
std_logic
;
s_buffer_eo
:
vme_buffer_eo
;
s_latch_oe
:
std_logic
;
s_dtack_oe
:
std_logic
;
end
record
;
type
t_FSM
is
record
s_memReq
:
std_logic
;
s_decode
:
std_logic
;
s_dtackOE
:
std_logic
;
s_mainDTACK
:
std_logic
;
s_buffer
:
t_VME_BUFFER
;
--s_dtackOE : std_logic;
--s_dataBuf : t_VME_BUFFER;
--s_addrBuf : t_VME_BUFFER;
--s_dataDir : std_logic;
...
...
@@ -80,12 +81,12 @@ package xvme64x_pack is
record
s_IACKOUT
:
std_logic
;
--s_DataDir : std_logic;
--s_DTACK_OE : std_logic;
s_buffer
:
t_VME_BUFFER
;
s_DTACK
:
std_logic
;
s_enableIRQ
:
std_logic
;
s_resetIRQ
:
std_logic
;
s_DSlatch
:
std_logic
;
s_DTACK_OE
:
std_logic
;
end
record
;
--_______________________________________________________________________________
...
...
@@ -237,6 +238,7 @@ package xvme64x_pack is
s_dataDir
=>
'0'
,
s_clk
=>
'0'
,
s_buffer_eo
=>
ADDR_BUFF
,
s_dtack_oe
=>
'0'
,
s_latch_oe
=>
'0'
);
-- Main Finite State machine signals default:
...
...
@@ -248,9 +250,9 @@ package xvme64x_pack is
constant
c_FSM_default
:
t_FSM
:
=
(
s_memReq
=>
'0'
,
s_decode
=>
'0'
,
s_dtackOE
=>
'0'
,
s_mainDTACK
=>
'1'
,
s_buffer
=>
c_buffer_default
,
--s_dtackOE => '0',
--s_dataDir => '0',
--s_dataOE => '0',
--s_addrDir => '0', -- during IACK cycle the ADDR lines are input
...
...
@@ -270,12 +272,12 @@ package xvme64x_pack is
constant
c_FSM_IRQ
:
t_FSM_IRQ
:
=
(
s_IACKOUT
=>
'1'
,
--s_DataDir => '0',
--s_DTACK_OE => '0',
s_buffer
=>
c_buffer_default
,
s_DTACK
=>
'1'
,
s_enableIRQ
=>
'0'
,
s_resetIRQ
=>
'1'
,
s_DSlatch
=>
'0'
,
s_DTACK_OE
=>
'0'
s_DSlatch
=>
'0'
);
-- CSR address:
...
...
@@ -484,7 +486,7 @@ function f_latchDS (clk_period : integer) return integer;
VME_IACKOUT_n_o
:
out
std_logic
;
VME_DTACK_n_o
:
out
std_logic
;
VME_DTACK_OE_o
:
out
std_logic
;
--
VME_DTACK_OE_o : out std_logic;
VME_Buffer_o
:
out
t_VME_BUFFER
;
MASTER_O
:
out
t_wishbone_master_out
;
...
...
@@ -546,7 +548,7 @@ function f_latchDS (clk_period : integer) return integer;
VME_RETRY_n_o
:
out
std_logic
;
VME_RETRY_OE_o
:
out
std_logic
;
VME_DTACK_n_o
:
out
std_logic
;
VME_DTACK_OE_o
:
out
std_logic
;
--
VME_DTACK_OE_o : out std_logic;
VME_BERR_o
:
out
std_logic
;
VME_ADDR_o
:
out
std_logic_vector
(
31
downto
1
);
VME_BUFFER_o
:
out
t_VME_BUFFER
;
...
...
@@ -915,7 +917,7 @@ function f_latchDS (clk_period : integer) return integer;
VME_IRQ_n_o
:
out
std_logic_vector
(
6
downto
0
);
VME_IACKOUT_n_o
:
out
std_logic
;
VME_DTACK_n_o
:
out
std_logic
;
VME_DTACK_OE_o
:
out
std_logic
;
--
VME_DTACK_OE_o : out std_logic;
VME_DATA_o
:
out
std_logic_vector
(
31
downto
0
);
--VME_DATA_DIR_o : out std_logic
VME_BUFFER_o
:
out
t_VME_BUFFER
...
...
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