... | ... | @@ -21,7 +21,10 @@ final goal is to achieve a data-throughput of one data per clock cycle. |
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The design strategy requires the accurate definition of very deep
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pipelined datapaths with concurrent accesses to external memory banks.
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In order to facilitate the management of concurrent external memory
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accesses, we have used a customized memory control unit.
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accesses, we have used a customized memory control
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unit.
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![](/uploads/2f760813454591b5245eba013657e2ad/output_features.png)
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This fine grain pipeline strategy adopted for the core increases the
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maximum clock frequency by reducing the largest path delay between the
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