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# The HiCCE wiki
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# The HiCCE wiki
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# HiCCE-128-FMC version 2
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## HiCCE-128-FMC version 2
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The second prototype of the HiCCE project.
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The second prototype of the HiCCE project.
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<p align="center">
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<p align="center">
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<img src= "/hicce-fmc-128/blob/c2b5d374f50fc6da6c9a77029bdc2f96615e10b3/Images/HiCCEv2_Top_image.jpg", width="200" >
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<img src= "https://ohwr.org/project/hicce-fmc-128/raw/master/Images/HiCCEv2_Top_image.jpg", width="200" >
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<img src= "https://ohwr.org/project/hicce-fmc-128/raw/master/Images/HiCCEv2_Bottom_image.jpg", width="250" >
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</p>
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</p>
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In the second version of the HiCCE-FMC-128 module, digital resistors used in the first prototype module to control the upper and lower limit of the bandpass filter on the Intan RHA2132 frontend chips were removed. The bandwidth was fixed to 1.0 Hz – 20 kHz.
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The current status is we got two copies of the first draft board, and
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We tested HiCCE-FMC-128 version 2 using a commercial low-cost FMC carrier based on a modern hybrid Zynq-7000 SoC device that integrates an FPGA fabric along with a dual-core 32-bits processor (ARM Cortex).
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<!-- The current status is we got two copies of the first draft board, and
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Andres and Maria Liz are validating it. During Andres' last stay, we
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Andres and Maria Liz are validating it. During Andres' last stay, we
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discussed a number of potential revisions to the
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discussed a number of potential revisions to the
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board.
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board.
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-->
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![](/uploads/6eb96051a31535077758e13b5761a637/IMG_1473_small.jpg)
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![](/uploads/6eb96051a31535077758e13b5761a637/IMG_1473_small.jpg)
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