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As an example I will describe White Rabbit Cores, which is a part of
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White Rabbit project. Hdlmake is there engaged fot synthesis makefiles
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generation.
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White Rabbit project. Hdlmake is there engaged in the synthesis
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makefiles generation. It is synthesized with ISE.
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Before going further it is recommended to clone WRC git repository
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(git@ohwr.org:hdl-core-lib/wr-cores.git).
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... | ... | @@ -21,3 +21,53 @@ kept. Let's analyze what can be found in the manifest: |
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modules = { "local" : [ "../../../top/spec_1_1/wr_core_demo" ] }
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Variable</strong></td>
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<td><strong>Value</strong></td>
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<td><strong>Meaning</strong></td>
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</tr>
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<tr class="even">
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<td>target</td>
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<td>xilinx</td>
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<td>Target vendor for the synthesis is Xilinx</td>
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</tr>
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<tr class="odd">
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<td>action</td>
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<td>synthesis</td>
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<td>Action for the makefile is synthesis</td>
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</tr>
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<tr class="even">
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<td>fetchto</td>
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<td>./../../ip_cores</td>
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<td>All fetched modules from the current manifest will be put in ../../../ip_cores</td>
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</tr>
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<tr class="odd">
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<td>syn_device</td>
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<td>xc6slx45t</td>
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<td>Part number to but put in the project file</td>
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</tr>
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<tr class="even">
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<td>syn_grade</td>
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<td>-3</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td>syn_package</td>
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<td>fgg484</td>
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<td>Package of the chosen part</td>
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</tr>
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<tr class="even">
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<td>syn_top</td>
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<td>spec_top</td>
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<td>Top design's entity</td>
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</tr>
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<tr class="odd">
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<td>syn_project</td>
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<td>spec_top_wrc.xise</td>
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<td>ISE p</td>
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</tr>
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</tbody>
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</table>
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