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# Project description
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The goal of the project is to provide HDL developers with tools, whose
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aim is to solve typical problems connected with simulation and
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synthesis.
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# Simulation
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For the time being we are attached to Modelsim as the best tool for HDL simulation. All of the scripts are intended to use this tool.
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When compiling VHDL files for simulation, one must ensure their correct
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order. In every project there is a dependency tree among files - one
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file makes use of data from an other file by e.g. including it. Each
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file may not be compiled until all files it is dependent on are
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compiled, otherwise the compilation process will fail. There are no
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major obstacles when simulating Xilinx projects. The Project Navigator
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can automatically generate a bash script using Modelsim for any project.
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The script ensures correct compilation order and that all dependencies
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will be met.
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For Altera there is no tool for this purpose delivered by the vendor.
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# Synthesis
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