... | @@ -2,7 +2,7 @@ |
... | @@ -2,7 +2,7 @@ |
|
|
|
|
|
## Rationale
|
|
## Rationale
|
|
|
|
|
|
Maintaining VHDL projects either for Altera or for Xilins is a source of
|
|
Maintaining VHDL projects either for Altera or for Xilinx is a source of
|
|
many problems. When using Modelsim for simulating VHDL designs there is
|
|
many problems. When using Modelsim for simulating VHDL designs there is
|
|
no tool for dependencies generation. The developer has to think up the
|
|
no tool for dependencies generation. The developer has to think up the
|
|
dependencies between files and modules, as well as compilation order, on
|
|
dependencies between files and modules, as well as compilation order, on
|
... | | ... | |