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modularity, scalability, use of revision control systems and code reuse.
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Hdlmake is free, open and distributed with GPL.
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## Hdlmake project
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- [FAQ](FAQ)
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- [Developer-Guidelines](Developer-Guidelines)
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## Features
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### Supported Tools
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<table>
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<tbody>
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<tr class="odd">
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<td><b> Tool </b></td>
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<td><b> Synthesis </b></td>
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<td>Simulation</td>
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</tr>
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<tr class="even">
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<td>Xilinx ISE</td>
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<td>Yes</td>
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<td>n.a.</td>
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</tr>
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<tr class="odd">
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<td>Xilinx PlanAhead</td>
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<td>Yes</td>
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<td>No</td>
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</tr>
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<tr class="even">
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<td>Altera Quartus</td>
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<td>Yes</td>
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<td>n.a.</td>
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</tr>
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<tr class="odd">
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<td>Microsemi (Actel) Libero</td>
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<td>Yes</td>
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<td>n.a.</td>
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</tr>
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<tr class="even">
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<td>Lattice Semi. Diamond</td>
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<td>Yes</td>
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<td>n.a.</td>
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</tr>
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<tr class="odd">
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<td>Xilinx ISim</td>
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<td>Yes</td>
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<td>n.a.</td>
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</tr>
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<tr class="even">
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<td>Mentor Graphics Modelsim</td>
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<td>n.a.</td>
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<td>Yes</td>
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</tr>
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<tr class="odd">
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<td>Aldec Active-HDL</td>
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<td>n.a.</td>
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<td>Yes</td>
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</tr>
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<tr class="even">
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<td>Icarus Verilog</td>
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<td>n.a.</td>
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<td>Verilog</td>
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</tr>
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<tr class="odd">
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<td>GHDL</td>
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<td>n.a.</td>
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<td>VHDL</td>
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</tr>
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</tbody>
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</table>
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## Documentation
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Hdlmake docs are written by using Sphinx and hosted in [Read the
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