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## Intro
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## Intro
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Bring the current master to a similar stage to the ISYP branch.
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## Docs
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## Docs
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It includes two pdf files that are not valid for current master -- they
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Command syntax and run arguments name/behavior have changed from ISYP to
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are isyp related.
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current master, but the documentation it's not well
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### In sources
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It includes two pdf files that are not valid for current master as they
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are ISYP related.
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- **hdlmake\_manual.pdf**: this is old, points to ISYP information. It
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only mentions VHDL supported, while some of the current hdlmake
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actions support Verilog, VHDL and even some other HDL languages such
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as System Verilog.
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- **hdlmake\_quick\_start.pdf**: this is old, related with ISYP.
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The source file in La(tex) format.
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- **hdlmake.tex**: this is supposed to be the actual user document
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specific for current Master code, but it seems to be targeted to
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ISYP again.
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### Wiki
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The ISYP and current Masted related info is mixed across the wiki.
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- [Manifest-variables-description](Manifest-variables-description):
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this is from ISYP. Some of the critical variables for current Master
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are not listed: e.g.
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syn\_tool
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- [Run-arguments-summary:Run-arguments-summary](https://www.ohwr.org/project/Run-arguments-summary/wikis):
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the argument syntax is from ISYP, but the argument set doesn't match
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with the actual code/binary.
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The source file should be upgraded.
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### Proposal
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Separation between older releases stuff and current master.
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- Compile all the stuff related with ISYP/v1.0 and set a clear wiki
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section for this stuff.
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- Write a new user document in both wiki and texinfo
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A full current feature set list with examples and parameter/options.
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A full current feature set list with examples and parameter/options.
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... | @@ -69,9 +106,18 @@ different tool specific actions: |
... | @@ -69,9 +106,18 @@ different tool specific actions: |
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*GHDL**: some work was made in a separate branch. This is not included
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*GHDL**: some work was made in a separate branch. This is not included
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in master and follows an older software design (2 years old).
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in master and follows an older software design (2 years old).
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Xilinx biased, no synthesis makefiles for Altera.
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### Proposal
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### Proposal
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Xilinx biased, no synthesis makefiles for Altera.
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Add a supported action table and a demo project / example.
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Add support for Makefile generation handling Quartus synthesis.
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## Simulation
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Each simulation makefile builds a run project / workspace and then
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specific.
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## Device Family Support
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## Device Family Support
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