... | ... | @@ -95,22 +95,11 @@ the hdlmake test folder under the **2014** repository branch. |
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The following table indicates the most important testground features:
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Operating System</strong></td>
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<td>Ubuntu 14.04 LTS "Trusty Tahr"</td>
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</tr>
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<tr class="even">
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<td><strong>Python Version</strong></td>
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<td>Python 2.7.6 (Python3 not supported)</td>
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</tr>
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<tr class="odd">
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<td><strong>Architecture</strong></td>
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<td>i386, amd64, armhf [1]</td>
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</tr>
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</tbody>
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</table>
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|**Operating System**|Ubuntu 14.04 LTS "Trusty Tahr"|
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|----|----|
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|**Python Version**|Python 2.7.6 (Python3 not supported)|
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|**Architecture**|i386, amd64, armhf [1]|
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- \[1\] All of those hdlmake actions not relying on a local
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ISE/Quartus install can be executed from an ARM based processor
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... | ... | @@ -129,25 +118,11 @@ The following table indicates the most important testground features: |
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### Brand biased feature set
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Action</strong></td>
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<td><strong>ISE (Xilinx)</strong></td>
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<td><strong>Quartus (Altera)</strong></td>
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</tr>
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<tr class="even">
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<td>Project Generation</td>
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<td>YES</td>
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<td>YES</td>
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</tr>
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<tr class="odd">
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<td>Synthesis</td>
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<td>YES</td>
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<td>NO</td>
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</tr>
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</tbody>
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</table>
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|**Action**|**ISE (Xilinx)**|**Quartus (Altera)**|
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|----|----|----|
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|Project Generation|YES|YES|
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|Synthesis|YES|NO|
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Xilinx ISE is the only supported tool for synthesis -- Altera Quartus
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synthesis not supported.
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... | ... | @@ -201,35 +176,13 @@ being handled. |
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### Tool coverage
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Tool</strong></td>
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<td><strong>VHDL</strong></td>
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<td><strong>Verilog</strong></td>
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</tr>
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<tr class="even">
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<td>ISIM</td>
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<td>YES</td>
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<td>YES</td>
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</tr>
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<tr class="odd">
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<td>Modelsim</td>
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<td>YES</td>
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<td>YES</td>
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</tr>
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<tr class="even">
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<td>Icarus Verilog</td>
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<td>NO</td>
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<td>YES</td>
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</tr>
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<tr class="odd">
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<td>GHDL</td>
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<td>PARTIAL [2]</td>
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<td>NO</td>
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</tr>
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</tbody>
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</table>
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|**Tool**|**VHDL**|**Verilog**|
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|----|----|----|
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|ISIM|YES|YES|
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|Modelsim|YES|YES|
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|Icarus Verilog|NO|YES|
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|GHDL|PARTIAL [2]|NO|
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*: some GHDL support work was made in a separate branch. This is not
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included in master and follows an older software design (2 years old).
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... | ... | @@ -262,61 +215,24 @@ discussed on hdlmake mailing list. |
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### Xilinx supported families
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Key</strong></td>
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<td><strong>Family</strong></td>
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</tr>
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<tr class="even">
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<td>XC6S</td>
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<td>Spartan6</td>
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</tr>
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<tr class="odd">
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<td>XC3S</td>
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<td>Spartan3</td>
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</tr>
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<tr class="even">
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<td>XC6V</td>
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<td>Virtex6</td>
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</tr>
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<tr class="odd">
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<td>XC5V</td>
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<td>Virtex5</td>
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</tr>
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<tr class="even">
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<td>XC4V</td>
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<td>Virtex4</td>
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</tr>
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<tr class="odd">
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<td>XC7K</td>
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<td>Kintex7</td>
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</tr>
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<tr class="even">
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<td>XC7A</td>
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<td>Artix7</td>
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</tr>
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</tbody>
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</table>
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|**Key**|**Family**|
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|----|----|
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|XC6S|Spartan6|
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|XC3S|Spartan3|
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|XC6V|Virtex6|
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|XC5V|Virtex5|
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|XC4V|Virtex4|
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|XC7K|Kintex7|
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|XC7A|Artix7|
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### Altera supported families
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Key</strong></td>
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<td><strong>Family</strong></td>
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</tr>
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<tr class="even">
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<td>EP2AGX</td>
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<td>Arria II GX</td>
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</tr>
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<tr class="odd">
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<td>EP3C</td>
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<td>Cyclone III</td>
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</tr>
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</tbody>
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</table>
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|**Key**|**Family**|
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|----|----|
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|EP2AGX|Arria II GX|
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|EP3C|Cyclone III|
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### Proposal
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... | ... | @@ -336,46 +252,17 @@ discussed on hdlmake mailing list. |
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These are the new features that are listed as not or partially
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implemented in the following wiki entry: [NewFeatures](NewFeatures).
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>N</strong></td>
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<td><strong>Name</strong></td>
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</tr>
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<tr class="even">
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<td>1</td>
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<td>Better HDLMAKE_COREDIR handling</td>
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</tr>
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<tr class="odd">
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<td>6</td>
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<td>Screen support for remote synthesis.</td>
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</tr>
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<tr class="even">
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<td>9</td>
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<td>Fetch modules to a single directory, whatever the structure of the project is.</td>
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</tr>
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<tr class="odd">
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<td>15</td>
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<td>Fix all OHWR issues</td>
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</tr>
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<tr class="even">
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<td>19</td>
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<td>Add finer control for synthesis stages</td>
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</tr>
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<tr class="odd">
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<td>20</td>
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<td>Arrange a separate repository with test projects</td>
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</tr>
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<tr class="even">
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<td>21</td>
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<td>Add support for Windows OS</td>
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</tr>
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<tr class="odd">
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<td>22</td>
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<td>No binary in repo</td>
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</tr>
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</tbody>
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</table>
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|**N**|**Name**|
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|----|----|
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|1|Better HDLMAKE_COREDIR handling|
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|6|Screen support for remote synthesis.|
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|9|Fetch modules to a single directory, whatever the structure of the project is.|
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|15|Fix all OHWR issues|
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|19|Add finer control for synthesis stages|
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|20|Arrange a separate repository with test projects|
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|21|Add support for Windows OS|
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|22|No binary in repo|
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### Proposal
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... | ... | @@ -406,3 +293,4 @@ branch: |
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12 May 2014
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