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# Project description
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Project to share generic HDL cores.
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## General project information
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To make cores more easy to share, they should be coded as described in
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the [Document](/project/hdl-core-lib/wikis/Documents/VHDL-coding-guidelines).
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This project covers the development of re-usable HDL cores for FPGAs.
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Although there are no strict rules on practices, there is an emerging
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coherency developing around the concept of Wishbone-based design. We
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collaborated in the update of the [Document](/project/hdl-core-lib/wikis/Documents/Wishbone-B4-Specification) to include a pipelined
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mode which enhances communication with high-latency high-throughput
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devices, such as DDR RAM controllers. Another important development is
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the [Wishbone slave
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generator](https://www.ohwr.org/project/wishbone-gen), which helps in
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the repetitive task of creating Wishbone slaves in VHDL and Verilog. For
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VHDL development, please use the [Document](/project/hdl-core-lib/wikis/Documents/VHDL-coding-guidelines).
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