... | ... | @@ -13,6 +13,6 @@ the repetitive task of creating Wishbone slaves in VHDL and Verilog. |
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*Rules & Policies:**
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- For VHDL development, please use the [Document](https://www.ohwr.org/project/hdl-core-lib/wikis/Documents/VHDL-coding-guidelines).
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- For VHDL development, please use the [Document](https://www.ohwr.org/project/vhdl-style/wikis/Documents/vhdl-coding-style).
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- For the rules of using the Git repos, see [HDL-Git-Rules](HDL-Git-Rules)
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