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Project to share generic HDL cores.
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Project to share generic HDL cores.
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## Detailed project informations
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## General project information
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To make cores more easy to share, they should be coded has described in
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To make cores more easy to share, they should be coded has described in
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the [VHDL coding
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the [VHDL coding
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guidelines](https://www.ohwr.org/27) .
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guidelines](https://www.ohwr.org/27) .
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## Wishbone slave core generator
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Wishbone slave core generator (wbgen2) is a Lua script for generating
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VHDL Wishbone slave cores from a register set description provided by
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the user. By the ”slave core” we mean a HDL entity which is connected to
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Wishbone bus on one side, and on the other side it provides ports for
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accessing memory mapped registers, FIFOs and RAMs.
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Sources and documentation are in SVN repository :
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[wbgen2\_sources](https://www.ohwr.org/repositories/browse/hdl-core-lib/trunk/software/wbgen2)
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Requires LUA 5.1.4+.
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