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# Project description
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This project covers the development of re-usable HDL cores for FPGAs,
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each of which is a separate sub-project (see [complete
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The Corelib project covers the development of re-usable HDL cores for
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FPGAs, each of which is a separate sub-project (see [complete
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list](https://www.ohwr.org/project/hdl-core-lib)). Although there are
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no strict rules on practices, there is an emerging coherency developing
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around the concept of Wishbone-based design. We collaborated in the
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