... | ... | @@ -18,10 +18,10 @@ the user. By the ”slave core” we mean a HDL entity which is connected to |
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Wishbone bus on one side, and on the other side it provides ports for
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accessing memory mapped registers, FIFOs and RAMs.
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Sources and documentation are in SVN repository :
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[wbgen2\_sources](https://www.ohwr.org/repositories/browse/hdl-core-lib/trunk/software/wbgen2)
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Sources and documentation are in SVN repository : [wbgen2
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sources](https://www.ohwr.org/repositories/browse/hdl-core-lib/trunk/software/wbgen2)
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Requires LUA 5.1.4+.
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Requires LUA 5.1.4+ [LUA website](http://www.lua.org/)
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