... | ... | @@ -6,17 +6,13 @@ list](https://www.ohwr.org/project/hdl-core-lib)). |
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Although there are no strict rules on practices, there is an emerging
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coherency developing around the concept of Wishbone-based design. We
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collaborated in the update of the [Document](/project/hdl-core-lib/wikis/Documents/Wishbone-B4-Specification) to include a pipelined
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mode which enhances communication with high-latency high-throughput
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devices, such as DDR RAM controllers.
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collaborated in the update of the [Document](https://ohwr.org/project/hdl-core-lib/wikis/Documents/Wishbone-B4-Specification) to include a pipelined mode which enhances communication with high-latency high-throughput devices, such as DDR RAM controllers.
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Another important development is the [Wishbone slave
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generator](https://www.ohwr.org/project/wishbone-gen), which helps in
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Another important development is the [Wishbone slave generator](https://www.ohwr.org/project/wishbone-gen), which helps in
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the repetitive task of creating Wishbone slaves in VHDL and Verilog.
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*Rules & Policies:**
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- For VHDL development, please use the [Document](/project/hdl-core-lib/wikis/Documents/VHDL-coding-guidelines).
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- For the rules of using the Git repos, see
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[HDL-Git-Rules](HDL-Git-Rules)
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- For VHDL development, please use the [Document](https://www.ohwr.org/project/hdl-core-lib/wikis/Documents/VHDL-coding-guidelines).
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- For the rules of using the Git repos, see [HDL-Git-Rules](HDL-Git-Rules)
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