|
# Flash a Xilinx device
|
|
# Flash a Xilinx FPGA
|
|
|
|
|
|
Connect JTAG to your SPECv4 as
|
|
Connect JTAG to your SPECv4 as
|
|
shown:
|
|
shown:
|
... | @@ -35,6 +35,20 @@ using the ISE Impact tool. When you get random dialogues asking for |
... | @@ -35,6 +35,20 @@ using the ISE Impact tool. When you get random dialogues asking for |
|
Now that your device is flashed, confirm that it working using the
|
|
Now that your device is flashed, confirm that it working using the
|
|
[White-Rabbit-Console](White-Rabbit-Console).
|
|
[White-Rabbit-Console](White-Rabbit-Console).
|
|
|
|
|
|
|
|
# Flash a Xilinx CPLD
|
|
|
|
|
|
|
|
Connect the XXX cable to the card as shown:
|
|
|
|
|
|
|
|
Given a working bit file (you can use
|
|
|
|
[Prebuilt-images](Prebuilt-images)), you program the EEPROM of the CPLD
|
|
|
|
using the ISE Impact tool.
|
|
|
|
|
|
|
|
- Launch impact
|
|
|
|
|
|
|
|
-
|
|
|
|
\*\!\!\!\*The CPLD has an internal EEPROM, is a non-volatile memory,
|
|
|
|
remember to erase it before reprogram.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
### Files
|
|
### Files
|
... | | ... | |