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The Wishbone master implements a master for the Wishbone interconnection
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bus. It transforms a PCIe write into a Wishbone write and a PCIe read
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into a Wishbone read. Only single word reads and writes are supported.
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PCI express bursts are divided in sigle reads and writes.
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PCI express bursts are divided in single reads and writes.
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Data are coming from the packet decoder. Wishbone signals are generated
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and the master waits for an acknowledge. The incoming requests are saved
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