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# Generic Cores Library (a.k.a. GenCores)
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# Generic Cores Library (a.k.a. GenCores)
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GenCores library provides a number of common VHDL components used in
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General Cores is a library of widely-used HDL cores. Please see the [readme](https://ohwr.org/project/general-cores/blob/master/README.md) file for the latest documentation. There is also a slightly outdated [user manual](https://www.ohwr.org/project/general-cores/wikis/Documents/General-cores-manual) which does not cover the latest cores added to the collection but which can provide valuable insight for the rest.
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various projects hosted in the OHR. The library comprises 3 packages:
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- `gencores_pkg` - simple cores (synchronizer chain, delay generator,
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pulse extender, PI controller, CRC generator, etc.)
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- `genram_pkg` - collection of platform-independent wrappers for RAMs
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and FIFOs provided by the FPGA vendors (currently supported: Altera
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Cyclone3, Arria 2 GX and Xilinx Spartan6/Virtex6)
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- `wishbone_pkg` - set of commonly used Wishbone modules (UART, SPI,
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I2C, Onewire, GPIO, Timer, Interrupt controller, LM32 CPU, Pipelined
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WB
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Interconnect)
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# Available cores (in [Repository](https://www.ohwr.org/project/general-cores/tree/master))
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## General purpose
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- `gc_arbitrated_mux` - round-robin arbitrated N to 1 data stream
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multiplexer
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- `gc_bicolor_led_ctrl` - small bicolor LED matrix controller
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- `gc_big_addrer` - Kogge-Stone parametrizable adder
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- `gc_crc_gen` - parametrizable CRC generator/checker
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- `gc_delay_gen` - parametrizable signal synchronous delay line
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- `gc_dual_pi_controller` - simple PI controller
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- `gc_dyn_glitch_filt` - dynamic glitch filter
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- `gc_extend_pulse` - pulse width extender
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- `gc_frequency_meter` - as the name says
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- `gc_fsm_watchdog` - watchdog unit for state machines
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- `gc_glitch_filt` - asynchronous input deglitcher
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- `gc_i2c_slave` - parametrizable I2C slave core
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- `gc_moving_average` - parametrizable moving average filter
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- `gc_prio_encoder` - priority encoder, one-hot output
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- `gc_pulse_synchronizer` - cross-clock domain pulse synchronizer,
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works with any pulse width
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- `gc_reset` - power on reset unit
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- `gc_rr_arbiter` - Round-Robin arbiter
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- `gc_serial_dac` - simple interface for DACs with SPI interface
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- `gc_sync_ffs` - 3-stage synchronizer flip flop chain
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- `gc_sync_register` - 3-stage synchronizer flip flop chain (multi-bit
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version)
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- `gc_word_packer` - packs data stream of one bit width into a stream
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of another bit width
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## Memories/FIFOs
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- `generic_dpram` - generic dual port RAM, offering single/dual clock
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option, multiple address conflict resolution methods and
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initialization from a file during synthesis/simulation.
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- `generic_spram` - generic single port ram RAM
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- `generic_sync_fifo` - generic FIFO queue, single-clock
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- `generic_async_fifo` - generic FIFO queue, independent read and
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write clocks
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- `generic_shiftreg_fifo` - generic small FIFO based on an FPGA
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inferred shift register
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## Wishbone cores
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- `wb_async_bridge` - Asynchronous CPU bus to Wishbone bridge
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- `wb_clock_crossing` - Cross clock domain bus pass-through
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- `wb_crossbar` - Pipelined (WBv4) interconnect/crossbar
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- `wb_dma` - DMA controller
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- `wb_dpram` - RAM block with two WB ports
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- `wb_gpio_port` - Simple GPIO port
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- `wb_i2c_bridge` - I2C slave to Wishbone bridge
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- `wb_i2c_master` - I2C master core
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- `wb_irq` - Message Signaled IRQ core
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- `wb_lm32` - LM32 Embedded RISC Processor core
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- `wb_onewire_master` - OneWire master core
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- `wb_serial_lcd` - Serial LCD core
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- `wb_simple_pwm` - Single-output PWM controller
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- `wb_simple_timer` - Trivial timer core
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- `wb_slave_adapter` - Pipelined\<-\>Classic Wishbone mode adapter
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- `wb_spi` - SPI Master core
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- `wb_spi_flash` - SPI Serial Flash Controller
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- `wb_uart` - Simple UART
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- `wb_vic` - Vectored Interrupt Controller
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-----
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# Documentation
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- [General-cores VHDL library](https://www.ohwr.org/project/general-cores/wikis/Documents/General-cores-manual)
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-----
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-----
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# Contacts
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# Contacts
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- [Tomasz Wlostowski](mailto:Tomasz.Wlostowski@cern.ch) - CERN
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- [Javier Serrano](mailto:Javier.Serrano@cern.ch) - CERN
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-----
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-----
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21 May 2015
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5 Sep 2023
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