... | ... | @@ -54,7 +54,7 @@ various projects hosted in the OHR. The library comprises 3 packages: |
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- `generic_shiftreg_fifo` - generic small FIFO based on an FPGA
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inferred shift register
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### Wishbone cores
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## Wishbone cores
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- `wb_async_bridge` - Asynchronous CPU bus to Wishbone bridge
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- `wb_clock_crossing` - Cross clock domain bus pass-through
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