... | @@ -42,3 +42,37 @@ various projects hosted in the OHR. The library comprises 3 packages: |
... | @@ -42,3 +42,37 @@ various projects hosted in the OHR. The library comprises 3 packages: |
|
- `gc_word_packer` - packs data stream of one bit width into a stream
|
|
- `gc_word_packer` - packs data stream of one bit width into a stream
|
|
of another bit width
|
|
of another bit width
|
|
|
|
|
|
|
|
## Memories/FIFOs
|
|
|
|
|
|
|
|
- `generic_dpram` - generic dual port RAM, offering single/dual clock
|
|
|
|
option, multiple address conflict resolution methods and
|
|
|
|
initialization from a file during synthesis/simulation.
|
|
|
|
- `generic_spram` - generic single port ram RAM
|
|
|
|
- `generic_sync_fifo` - generic FIFO queue, single-clock
|
|
|
|
- `generic_async_fifo` - generic FIFO queue, independent read and
|
|
|
|
write clocks
|
|
|
|
- `generic_shiftreg_fifo` - generic small FIFO based on an FPGA
|
|
|
|
inferred shift register
|
|
|
|
|
|
|
|
### Wishbone cores
|
|
|
|
|
|
|
|
- `wb_async_bridge` - Asynchronous CPU bus to Wishbone bridge
|
|
|
|
- `wb_clock_crossing` - Cross clock domain bus pass-through
|
|
|
|
- `wb_crossbar` - Pipelined (WBv4) interconnect/crossbar
|
|
|
|
- `wb_dma` - DMA controller
|
|
|
|
- `wb_dpram` - RAM block with two WB ports
|
|
|
|
- `wb_gpio_port` - Simple GPIO port
|
|
|
|
- `wb_i2c_bridge` - I2C slave to Wishbone bridge
|
|
|
|
- `wb_i2c_master` - I2C master core
|
|
|
|
- `wb_irq` - Message Signaled IRQ core
|
|
|
|
- `wb_lm32` - LM32 Embedded RISC Processor core
|
|
|
|
- `wb_onewire_master` - OneWire master core
|
|
|
|
- `wb_serial_lcd` - Serial LCD core
|
|
|
|
- `wb_simple_pwm` - Single-output PWM controller
|
|
|
|
- `wb_simple_timer` - Trivial timer core
|
|
|
|
- `wb_slave_adapter` - Pipelined\<-\>Classic Wishbone mode adapter
|
|
|
|
- `wb_spi` - SPI Master core
|
|
|
|
- `wb_spi_flash` - SPI Serial Flash Controller
|
|
|
|
- `wb_uart` - Simple UART
|
|
|
|
- `wb_vic` - Vectored Interrupt Controller
|
|
|
|
|