... | ... | @@ -43,120 +43,54 @@ the board, coupled with its flexible architecture, mean that it can |
|
|
easily be adapted for use in many different applications where radiation
|
|
|
tolerance is a requirement.
|
|
|
|
|
|
/project/white-rabbit/uploads/11578355de03b7cc74a366b23b508c48/svectop_s.png
|
|
|
*SVEC V1 production board** - [block
|
|
|
diagram](https://www.ohwr.org/project/svec/uploads/e234fa371e49b0d8f0311cdd236df19c/Block.png)
|
|
|
|
|
|
## Main Features
|
|
|
|
|
|
- VME64x interface
|
|
|
- Two Low-Pin Count FMC slots
|
|
|
- Vadj fixed to 2.5V
|
|
|
- No dedicated clock signals from Carrier to FMC (as only
|
|
|
available on HPC pins and use LPC)
|
|
|
- FMC connectivity: all 34 differential pairs connected, 1 GTP
|
|
|
transceiver with clock, 2 clock pairs, JTAG
|
|
|
- Xilinx FPGAs
|
|
|
- Application FPGA: Spartan-6 XC6SLX150T-3FGG900C
|
|
|
- Direct connection to all resources such as VME64x, memories
|
|
|
and FMC connectors
|
|
|
- System FPGA: Spartan-6 XC6SLX9-2FTG256C
|
|
|
- Provides VME bootloader, early oscillator/PLL config
|
|
|
- Configuration Flash memory for both Main FPGA and
|
|
|
Application FPGA configuration
|
|
|
- FPGA configuration
|
|
|
- From SPI flash or via VME
|
|
|
- Clocking resources
|
|
|
- 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100
|
|
|
MHz (Silicon Labs Si570, freely usable)
|
|
|
- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662,
|
|
|
used by [White Rabbit PTP
|
|
|
core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
|
|
|
- 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662,
|
|
|
used by [White Rabbit PTP
|
|
|
core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
|
|
|
- 2x low-jitter frequency synthesizer/fanout (TI CDCM61004, fixed
|
|
|
configuration, Fout=125 MHz, used by [White Rabbit PTP
|
|
|
core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
|
|
|
- On-board memories
|
|
|
- 2x 256 MByte (2 Gbit) DDR3 (16-bit bus, MT41J128M16JT-125)
|
|
|
- 1x 128 Mbit SPI flash for FPGA firmware storage (M25P128-VME6GB)
|
|
|
- 64kbit EEPROM connected for storing application parameters
|
|
|
(24AA64T-I/MC)
|
|
|
- 1x I2C configuration EEPROM (24LC64)
|
|
|
- Miscellaneous
|
|
|
- On-board thermometer IC (DS18B20U+)
|
|
|
- Unique 64-bit identifier (DS18B20U+)
|
|
|
- Front panel
|
|
|
- 1x SFP port ([White
|
|
|
Rabbit](https://www.ohwr.org/project/white-rabbit/wikis/)
|
|
|
compatible)
|
|
|
- 4x LEMO/SMC programmable I/Os capable of driving 3.3V @ 50 ohm
|
|
|
- 2x mini displayPort connectors for high-speed serial GTP links
|
|
|
(not for video)
|
|
|
- 8x Programmable LED
|
|
|
- Reset push button
|
|
|
- Internal connectors
|
|
|
- VME P2 connector provides access to a Rear Transition Module
|
|
|
(compatible to
|
|
|
[VFC](https://www.ohwr.org/project/fmc-vme-carrier/wiki))
|
|
|
- 40 user defined single ended (Vcco=2.5V) signals (or 20 LVDS
|
|
|
pairs) connected to the Application FPGA
|
|
|
- 2x 125 MHz LVDS clocks provided to the RTM
|
|
|
- Xilinx-style JTAG connector
|
|
|
- Internal mini USB 2.0 High Speed connector for stand-alone
|
|
|
applications (CP2103)
|
|
|
- Optional features, check with vendor
|
|
|
- Internal 2 x SATA connector for stand-alone PCI Express
|
|
|
connectivity (clock + data)
|
|
|
- Internal 4 x UFL connectors with low-jitter clock for FMC cards
|
|
|
- Internal additional USB 2.0 on 4-pin header (FT2232HL)
|
|
|
- Battery for secure storage of FPGA configuration data
|
|
|
- Stand-alone features
|
|
|
- External supply connector (3.3V, 5V) on internal SATA
|
|
|
connector
|
|
|
- PCIe interface on internal SATA connector
|
|
|
- 10-layer PCB
|
|
|
/3829
|
|
|
*VFC-HPC V1.0** (development version with SRAM)
|
|
|
|
|
|
## Main features
|
|
|
|
|
|
- Altera Arria V GX FPGA (5AGXMB1G4F40C4N)
|
|
|
- HPC FMC slot
|
|
|
- Fully populated LA, HA & HB banks
|
|
|
- 10 gigabit lanes connected to FPGA transceivers
|
|
|
- Programmable Vadj
|
|
|
- 6 SFP+ running up to 6.5Gbps
|
|
|
- 4 "application" SFPs for GBT connections
|
|
|
- 2 "system" SFPs for BST/White Rabbit & Ethernet
|
|
|
- 40 single ended (or 20 LVDS) connections to VME P2 available for
|
|
|
rear transition modules
|
|
|
- 30 single ended connections to VME64x P0 to support clock & trigger
|
|
|
distribution in (custom) BI LHC VME crates
|
|
|
- Flexible clocking resources
|
|
|
- Si570 10-280MHz programmable oscillator
|
|
|
- ADN2814 CDR for BST reception
|
|
|
- 125MHz & 20MHz VCXOs for White Rabbit support
|
|
|
- Si5338 clock synthesizer
|
|
|
- DDR3 slot supporting up to 8GB SODIMMs
|
|
|
- Front panel connectivity:
|
|
|
- 6 SFP+ cages
|
|
|
- 4 LEMO-00 general purpose I/O
|
|
|
- 8 user LEDs
|
|
|
- 12 layer PCB
|
|
|
|
|
|
-----
|
|
|
|
|
|
## Project information
|
|
|
|
|
|
- Official production documentation:
|
|
|
[EDA-03168-V1](http://edms.cern.ch/nav/eda-03168)
|
|
|
- [Specifications (User
|
|
|
Guide)](http://www.janztec.com/fileadmin/downloads/manuals/manual_svec_hardware.pdf)
|
|
|
(Janz Tec)
|
|
|
- [Block diagram](https://www.ohwr.org/project/svec/uploads/e234fa371e49b0d8f0311cdd236df19c/Block.png)
|
|
|
- [CERN specific information](CERN)
|
|
|
- [Users](Users)
|
|
|
- [Software](Software)
|
|
|
- [Standard Gateware](https://www.ohwr.org/project/svec/wikis/documents) (and
|
|
|
[how to use it](https://www.ohwr.org/project/svec/wikis/Documents/SVEC-Gateware-Manual))
|
|
|
- [Frequently Asked Questions](FAQ)
|
|
|
- Official design data [EDMS
|
|
|
EDA-03133](https://edms.cern.ch/nav/EDA-03133)
|
|
|
- LHC equipment name: XXXXX
|
|
|
- Schematic diagram: xxx
|
|
|
- Overview presentation: xxx
|
|
|
- Bill of material: xxx
|
|
|
- [Manufacturing test suite](TestSuite)
|
|
|
|
|
|
-----
|
|
|
|
|
|
## [Releases](Releases)
|
|
|
|
|
|
*Latest:**
|
|
|
|
|
|
- Hardware: v1.0 -
|
|
|
[EDA-02530-V3-0](https://edms.cern.ch/nav/EDA-02530-V3-0)
|
|
|
|
|
|
-----
|
|
|
|
|
|
## Contacts
|
|
|
|
|
|
### Commercial producers
|
|
|
### Users
|
|
|
|
|
|
- [SVEC - BO-FVM-SVEC0](http://www.janztec.com/en/vme64xsvec.html)
|
|
|
[Janz Tec AG](http://www.janztec.com/en/), Germany
|
|
|
- [List of users of the VFC-HD](users)
|
|
|
|
|
|
### General question about project
|
|
|
### Contact
|
|
|
|
|
|
- [Manoel Barros Marin](mailto:manoel.barros.marin@cern.ch) - CERN
|
|
|
(BE-BI-QP)
|
|
|
- [Andrea Boccardi](https://www.ohwr.org/users/11) - CERN
|
|
|
|
|
|
-----
|
|
|
|
... | ... | @@ -170,16 +104,16 @@ diagram](https://www.ohwr.org/project/svec/uploads/e234fa371e49b0d8f0311cdd236df |
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>03-02-2015</td>
|
|
|
<td>First version of GEFE specification written.</td>
|
|
|
<td>Inclusion of project on OHWR</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>04-07-2015</td>
|
|
|
<td>OHWR repository Wiki update.</td>
|
|
|
<td>First OHWR Wiki update.</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|
|
|
-----
|
|
|
|
|
|
6 July 2015
|
|
|
Manoel Barros Marin - 04 July 2015
|
|
|
|