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# FPGA Configuration Space Specification
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This project is an effort to introduce a configuration space
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specification for Wishbone peripherals that allows them to be
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auto-probed by operating system drivers.
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specification for
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internal FPGA buses (interconnects, crossbars). Our initial target is
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Wishbone,
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but the specificationis generic.
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The following are currently available in the project repository:
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The aim is being able to enumerate the cores that are live in the
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current
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fpga binary, either from the host computer or from the internal
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soft-core
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CPU in the FPGA itself.
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- Specification
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- Wishbone Simulation
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The current specification is already in use in some of our designs.
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## Specification
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The initial draft of the specification is available as a PDF in the
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project repository. You can download the latest version
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[here](https://www.ohwr.org/project/fpga-config-space/blob/master/sdwb.pdf).
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The specification is available in PDF format,together with the header
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file from [here](https://www.ohwr.org/project/fpga-config-space/wikis/Documents/SDB-specification-June-2012)
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It has been built from the repository of this project, so you can get
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the git tree instead and run Latex on it.
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## Wishbone Simulation
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## Code
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The Wishbone simulation is a set of drivers that allow for the
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simulation of the configuration space structures and allow for
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understanding how the driver model will work. The simulation currently
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consists of:
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The implementation as VHDL is part of the respective projects
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(currently, Etherbone and White Rabbit Core).
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- **Wishbone Bus Driver** This creates a Linux Wishbone bus (can be
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seen under */sys/bus/wb*).
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- **Wishbone Peripheral Drivers** These fake Wishbone drivers simply
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register to specific Wishbone ID's and print debug messages when
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loaded.
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- **Spec Board Driver** This is a fake PCI driver for the spec board
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that takes a firmware file (representing the Wishbone address space)
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and registers any Wishbone peripherals it finds.
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You can find the code for the simulation
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[here](https://www.ohwr.org/project/fpga-config-space/tree/master/simulation).
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You can download binary versions of the drivers
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[here](https://www.ohwr.org/project/fpga-config-space/uploads/d3da0ea576cb42194d9b1e375351108b/wbonesim.tgz) (not
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recommended as it is kernel-version-specific and may be outdated with
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respect to the repository).
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## Links
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[SDWB Specification
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(PDF)](https://www.ohwr.org/854)
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[Wishbone Simulation
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(Source)](https://www.ohwr.org/project/fpga-config-space/tree/master/simulation)
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Core for the Linux kernel (both as a bus driver and a file system
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driver) is being written. In the repository
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you find the initial work that has been done months ago as a proof of
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concept.
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## Status
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| ... | ... | @@ -65,6 +51,10 @@ respect to the repository). |
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<td>10-05-2011</td>
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<td>Added code for wishbone simulator (source code available in Repository or Files section)</td>
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</tr>
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<tr class="odd">
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<td>21-06-2012</td>
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<td>After long discussions, the specification is published</td>
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</tr>
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</tbody>
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</table>
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