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# FPGA Configuration Space Specification
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This project is an effort to introduce a configuration space
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specification for Wishbone peripherals that allows them to be
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auto-probed by operating system drivers.
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The following are currently available in the project repository:
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- Specification
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- Wishbone Simulation
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## Specification
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The initial draft of the specification is available as a PDF in the
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project repository. You can download the latest version
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[here](https://www.ohwr.org/project/fpga-config-space/blob/master/sdwb.pdf).
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## Wishbone Simulation
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The Wishbone simulation is a set of drivers that allow for the
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simulation of the configuration space structures and allow for
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understanding how the driver model will work. The simulation currently
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consists of:
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- **Wishbone Bus Driver** This creates a Linux Wishbone bus (can be
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seen under */sys/bus/wb*).
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- **Wishbone Peripheral Drivers** These fake Wishbone drivers simply
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register to specific Wishbone ID's and print debug messages when
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loaded.
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- **Spec Board Driver** This is a fake PCI driver for the spec board
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that takes a firmware file (representing the Wishbone address space)
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and registers any Wishbone peripherals it finds.
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You can find the code for the simulation
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[here](https://www.ohwr.org/project/fpga-config-space/tree/master/simulation).
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You can download binary versions of the drivers
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[here](https://www.ohwr.org/project/fpga-config-space/uploads/d3da0ea576cb42194d9b1e375351108b/wbonesim.tgz) (not
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recommended as it is kernel-version-specific and may be outdated with
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respect to the repository).
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