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This project is an effort to introduce a configuration space
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This project is an effort to introduce a configuration space
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specification for internal FPGA buses (interconnects, crossbars). Our
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specification for internal FPGA buses (interconnects, crossbars). Our
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initial target is Wishbone, but the specification is generic.
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initial target is Wishbone, but the specification is generic. The output
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of this project is called SDB (self describing bus) even if the project
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(thus the repository) is called fpga-config-space.
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The aim is being able to enumerate the cores that are live in the
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SDB allows to enumerate the cores that are live in the current fpga
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current fpga binary, either from the host computer or from the internal
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binary, either from the host computer or from the internal soft-core CPU
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soft-core CPU in the FPGA itself.
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in the FPGA itself.
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The current specification is already in use in some of our designs.
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The current specification is already in use in some of our designs. And
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we have some [sdb implementation
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[sdb implementation guidelines](sdb-implementation-guidelines)
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guidelines](sdb-implementation-guidelines)
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## Specification
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## Specification
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The [specification is available in PDF
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Version 1.0 of SDB the specification is available in [PDF
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format](https://www.ohwr.org/project/fpga-config-space/wikis/Documents/SDB-specification-June-2012), together with the header
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format](https://www.ohwr.org/project/fpga-config-space/wikis/Documents/SDB-specification-June-2012), together with the header
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file.
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file.
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It has been built from the repository of this project, so you can get
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It has been built from the repository of this project, so you can get
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the git tree instead and run Latex on it.
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the git tree instead and run Latex on it.
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## Interrupt support
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We chose, for the time being, to not describe interrupts. After some
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drafts for one such description, Wesley Terpstra
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explained why legacy interrupts should be avoided in a SoC design and
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MSI-like interrupts don't need an external description.
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His complete reasoning is here: [Interrupts](Interrupts)
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## Code
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## Code
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The implementation as VHDL is part of the respective projects
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The implementation as VHDL is part of the respective projects
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(currently, Etherbone and White Rabbit Core).
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(currently, Etherbone and White Rabbit Core).
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Core for the Linux kernel (both as a bus driver and a file system
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Code for the Linux kernel (both as a bus driver and a file system
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driver) is being written. In the repository you find the initial work
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driver) is being written. Available code
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that has been done months ago as a proof of concept.
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is part of this repository, but it's still work in progress.
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## Status
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## Status
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