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 # FPGA Configuration Space Specification
 
 This project is an effort to introduce a configuration space
-specification for  
-internal FPGA buses (interconnects, crossbars). Our initial target is
-Wishbone,  
-but the specificationis generic.
+specification for internal FPGA buses (interconnects, crossbars). Our
+initial target is Wishbone, but the specification is generic.
 
 The aim is being able to enumerate the cores that are live in the
-current  
-fpga binary, either from the host computer or from the internal
-soft-core  
-CPU in the FPGA itself.
+current fpga binary, either from the host computer or from the internal
+soft-core CPU in the FPGA itself.
 
 The current specification is already in use in some of our designs.
 
 ## Specification
 
-The specification is available in PDF format,together with the header
-file from [here](https://www.ohwr.org/project/fpga-config-space/wikis/Documents/SDB-specification-June-2012)  
+The [specification is available in PDF
+format](https://www.ohwr.org/project/fpga-config-space/wikis/Documents/SDB-specification-June-2012), together with the header
+file.  
 It has been built from the repository of this project, so you can get
 the git tree instead and run Latex on it.
 
@@ -27,9 +24,8 @@ The implementation as VHDL is part of the respective projects
 (currently, Etherbone and White Rabbit Core).
 
 Core for the Linux kernel (both as a bus driver and a file system
-driver) is being written. In the repository  
-you find the initial work that has been done months ago as a proof of
-concept.
+driver) is being written. In the repository you find the initial work
+that has been done months ago as a proof of concept.
 
 ## Status
 
@@ -58,3 +54,5 @@ concept.
 </tbody>
 </table>
 
+-----
+