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VME FMC Carrier VFC
Commits
2e4547c8
Commit
2e4547c8
authored
Feb 08, 2011
by
Andrea Boccardi
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SRAM int changes
parent
dc468174
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2 changed files
with
24 additions
and
21 deletions
+24
-21
ApplicationFpga.v
trunk/hdl/design/ApplicationFpga.v
+9
-9
WbToCy7c1470.v
trunk/hdl/design/WbToCy7c1470.v
+15
-12
No files found.
trunk/hdl/design/ApplicationFpga.v
View file @
2e4547c8
...
...
@@ -165,7 +165,7 @@ WbToCy7c1470 i_Sram1Controller(
.
SramBws_onb4
(
Sram1Bws_nb4
))
;
/*
wire
[
20
:
0
]
AdrSram2Controller
=
{
2'b0
,
Adr_b21
[
18
:
0
]
};
WbToCy7c1470
i_Sram2Controller
(
...
...
@@ -184,16 +184,16 @@ WbToCy7c1470 i_Sram2Controller(
.
SramWe_on
(
Sram2We_n
)
,
.
SramOe_on
(
Sram2Oe_n
)
,
.
SramBws_onb4
(
Sram2Bws_nb4
))
;
*/
assign
AckSram2Controller
=
1'b0
;
assign
Sram2Data_b36
=
DebugReg1
[
31
]
?
{
4'b0
,
DebugReg0
}
:
36
'
hz
;
assign
Sram2Address_b21
=
DebugReg1
[
20
:
0
]
;
assign
Sram2Clk_k
=
Clk_k
;
assign
Sram2We_n
=
~
DebugReg1
[
31
]
;
assign
Sram2Oe_n
=
DebugReg1
[
31
]
;
assign
Sram2Bws_nb4
=
4'h0
;
//assign AckSram2Controller = 1'b0;
//assign Sram2Data_b36 = DebugReg1[31] ? {4'b0, DebugReg0} : 36'hz;
//assign Sram2Address_b21 = DebugReg1[20:0];
//assign Sram2Clk_k = Clk_k;
//assign Sram2We_n = ~DebugReg1[31];
//assign Sram2Oe_n = DebugReg1[31];
//assign Sram2Bws_nb4 = 4'h0;
Generic4InputRegs
DebugInRegs
(
.
Rst_irq
(
Rst_rq
)
,
...
...
trunk/hdl/design/WbToCy7c1470.v
View file @
2e4547c8
...
...
@@ -12,37 +12,40 @@ module WbToCy7c1470 (
inout
[
35
:
0
]
SramData_iob36
,
output
reg
[
20
:
0
]
SramAddress_ob21
,
output
SramClk_ok
,
output
SramWe_on
,
output
reg
SramWe_on
,
output
SramOe_on
,
output
[
3
:
0
]
SramBws_onb4
)
;
reg
[
4
:
0
]
ReadCycle_d
;
reg
[
31
:
0
]
DatI_db32
[
2
:
0
]
;
reg
[
3
:
0
]
WriteCycle_d
;
reg
[
1
:
0
]
WriteCycle_d
;
reg
[
1
:
0
]
SramWe_d
;
wire
ReadCycle_a
=
Cyc_i
&&
Stb_i
&&
~
We_i
;
wire
WriteCycle_a
=
Cyc_i
&&
Stb_i
&&
We_i
;
always
@
(
posedge
Clk_ik
)
ReadCycle_d
<=
{
ReadCycle_d
[
3
:
0
]
,
ReadCycle_a
};
always
@
(
posedge
Clk_ik
)
ReadCycle_d
<=
#
1
{
ReadCycle_d
[
3
:
0
]
,
ReadCycle_a
};
assign
Ack_oa
=
WriteCycle_a
||
(
ReadCycle_a
&&
ReadCycle_d
[
3
])
;
assign
SramOe_on
=
1'b0
;
//~ReadCycle_d[2
];
assign
SramOe_on
=
SramWe_d
[
1
]
;
always
@
(
posedge
Clk_ik
)
SramAddress_ob21
<=
Adr_ib21
;
always
@
(
posedge
Clk_ik
)
SramAddress_ob21
<=
#
1
Adr_ib21
;
always
@
(
posedge
Clk_ik
)
WriteCycle_d
<=
{
WriteCycle_d
[
2
:
0
]
,
WriteCycle_a
};
always
@
(
posedge
Clk_ik
)
WriteCycle_d
<=
#
1
{
WriteCycle_d
[
0
]
,
WriteCycle_a
};
assign
SramWe_on
=
~
(
WriteCycle_d
[
1
:
0
]
==
2'b01
)
;
always
@
(
negedge
Clk_ik
)
SramWe_on
<=
#
1
~
(
WriteCycle_d
[
1
:
0
]
==
2'b01
)
;
always
@
(
negedge
Clk_ik
)
SramWe_d
<=
#
1
{
SramWe_d
[
0
]
,
~
SramWe_on
};
always
@
(
posedge
Clk_ik
)
begin
DatI_db32
[
2
]
<=
DatI_db32
[
1
]
;
DatI_db32
[
1
]
<=
DatI_db32
[
0
]
;
DatI_db32
[
0
]
<=
Dat_ib32
;
DatI_db32
[
2
]
<=
#
1
DatI_db32
[
1
]
;
DatI_db32
[
1
]
<=
#
1
DatI_db32
[
0
]
;
DatI_db32
[
0
]
<=
#
1
Dat_ib32
;
end
assign
SramData_iob36
=
(
WriteCycle_d
[
3
:
2
]
==
2'b01
)
?
{
4'h0
,
DatI_db32
[
2
]
}
:
36
'
hz
;
assign
SramData_iob36
=
SramWe_d
[
1
]
?
{
4'h0
,
DatI_db32
[
2
]
}:
36
'
hz
;
always
@
(
posedge
Clk_ik
)
if
(
ReadCycle_d
[
3
:
2
]
==
2'b01
)
Dat_ob32
<=
SramData_iob36
;
always
@
(
posedge
Clk_ik
)
if
(
ReadCycle_d
[
3
:
2
]
==
2'b01
)
Dat_ob32
<=
#
1
SramData_iob36
;
assign
SramClk_ok
=
Clk_ik
;
...
...
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