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# Meeting20090618
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- The Application FPGA should be connected also to the P2 connector's
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user pins.
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- Some of the P2 user pins will also be connected to unused FMC
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connector pins to be able to reroute analog signals from P0 to P2.
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- The analog footprint of our existing mezzanine should be
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investigated to see if it is possible for BI to use the standard FMC
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form factor. \<= action BI mezzanine developers and Andrea
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- A 3 FPGA solution has been suggested by Christos as an alternative
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to a 2 FPGA system. The pros and cons of such solution should be
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investigated \<= Action Christos, Andrea, Javier, Pablo
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- It was requested by Ralph to have a TCP-HTTP server on board. The
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case of use and the implication of this should be investigated \<=
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action Ralph for
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justification, Andrea + TB + CO for decision
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- It was proposed by David to have a DSP on board \<= action David for
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justification, Andrea + TB + CO for decision
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- In the current proposal the JTAG and I2C busses to the mezzanine
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were controlled by the system FPGA. It was requested to have the
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possibility to deisy chain it with the other board components and
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namely the system and te application FPGA. \<= action David for
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justification, Andrea + TB + CO for decision
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- On the prototype of the board the power supplies originally coming
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from the P0 connectors will be generated on board to evaluate their
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quality in this configuration. The possibility to bypass the
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generation modules and get the PS from the P0 will be assured by 0Ω
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resistors networks
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- The possibility to have a stricter symmetry between the VME and PCIe
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carriers should be investigated to see if it could lead to a 1 to 1
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sharing of the firmware. \<= action Andrea, Pablo, Javier
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### Files
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* [VMEFMC.pdf](/uploads/82ee8e7db14a796907ed712330aa9f1f/VMEFMC.pdf) |
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\ No newline at end of file |