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@@ -77,21 +77,21 @@
 <td>All active components ordered.</td>
 </tr>
 <tr class="even">
+<td>23-06-2010</td>
+<td>Layout files received and being reviewed.</td>
+</tr>
+<tr class="odd">
 <td>05-07-2010</td>
 <td>PCB layout review held.</td>
 </tr>
-<tr class="odd">
+<tr class="even">
 <td>09-08-2010</td>
 <td>PCB layout good for production.</td>
 </tr>
-<tr class="even">
+<tr class="odd">
 <td>01-09-2010</td>
 <td>Simulation started. Many troubles getting connectivity files out of schematics. Redo by hand.</td>
 </tr>
-<tr class="odd">
-<td>23-06-2010</td>
-<td>Layout files received and being reviewed.</td>
-</tr>
 <tr class="even">
 <td>15-09-2010</td>
 <td>PCB being produced at CERN. Expect assembled boards by mid October.</td>
@@ -110,23 +110,23 @@ One assembled board will arrive in a week.</td>
 <td>1st prototype received, waiting for the front panel.</td>
 </tr>
 <tr class="even">
-<td>8-11-2010</td>
+<td>08-11-2010</td>
 <td>1st prototype powered: 3 DC/DC are not working.</td>
 </tr>
 <tr class="odd">
-<td>9-11-2010</td>
+<td>09-11-2010</td>
 <td>2nd and 3rd prototype received: one powered and no issues on the PS this time</td>
 </tr>
 <tr class="even">
 <td>17-12-2010</td>
-<td>Test code loaded in the System FPGA and PROM programmed. JTAG and PROM loading are working.</td>
+<td>Test code loaded in the System FPGA and PROM programmed. JTAG and PROM loading are working. VME access OK.</td>
 </tr>
 </tbody>
 </table>
 
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-Andrea Boccardi, Erik van der Bij - 15 October 2010
+Andrea Boccardi, Erik van der Bij - 20 December 2010