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...@@ -70,130 +70,38 @@ VFC](users) ...@@ -70,130 +70,38 @@ VFC](users)
## Status ## Status
<table> |**Date**|**Event**|
<tbody> |----|----|
<tr class="odd"> |03-08-2009|[Functional specification](https://www.ohwr.org/project/fmc-vme-carrier/repository/entry/trunk/documentation/specifications/VFC_FunctionalSpecifications.pdf) written.|
<td><strong>Date</strong></td> |24-03-2010|PCB layout started|
<td><b> Event </b></td> |10-05-2010|Vadj fixed to 2.5V for FMC slot 2 to solve problems with bank power supplies.|
</tr> |11-05-2010|All active components ordered.|
<tr class="even"> |23-06-2010|Layout files received and being reviewed.|
<td>03-08-2009</td> |05-07-2010|PCB layout review held.|
<td><a href="https://www.ohwr.org/project/fmc-vme-carrier/repository/entry/trunk/documentation/specifications/VFC_FunctionalSpecifications.pdf">Functional specification</a> written.</td> |09-08-2010|PCB layout good for production.|
</tr> |01-09-2010|Simulation started. Many troubles getting connectivity files out of schematics. Redo by hand.|
<tr class="odd"> |15-09-2010|PCB being produced at CERN. Expect assembled boards by mid October.|
<td>24-03-2010</td> |06-10-2010|Two PCB's being assembled. A third one will come later.|
<td>PCB layout started</td> |15-10-2010|Problem with solder mask for 0402 capacitors under BGA detected. PCB specification will be changed.|
</tr> |19-10-2010|1st prototype received, waiting for the front panel.|
<tr class="even"> |08-11-2010|1st prototype powered: 3 DC/DC are not working.|
<td>10-05-2010</td> |09-11-2010|2nd and 3rd prototype received: one powered and no issues on the PS this time|
<td>Vadj fixed to 2.5V for FMC slot 2 to solve problems with bank power supplies.</td> |17-12-2010|Test code loaded in the System FPGA and PROM programmed. JTAG and PROM loading are working. VME access OK.|
</tr> |11-04-2011|Ten additional boards produced. Two reworked and work, but have JTAG issues. Eight still need rework.|
<tr class="odd"> |11-04-2011|Modifications to layout required. Can start in two to three weeks time.|
<td>11-05-2010</td> |07-06-2011|Start of sprint to debug the hardware design. 4 engineers intensively working on it, following the scrum methodology.|
<td>All active components ordered.</td> |24-06-2011|End of sprint to debug hardware design. Uncovered 18 Issues. DDR3 memory and DDS not debugged yet.|
</tr> |10-08-2011|New version of schematics ready.|
<tr class="even"> |16-08-2011|Schematics design review held [review16082011](review16082011). The design office will layout from 24 August on.|
<td>23-06-2010</td> |13-09-2011|Schematics still being updated. The design office will layout from 19 September on.|
<td>Layout files received and being reviewed.</td> |06-10-2011|V2 layout ready. Needs schematics and PCB review.|
</tr> |18-10-2011|V2 schematics and PCB review held.|
<tr class="odd"> |25-10-2011|Will produce 20 PCBs. First only 10 will be assembled.|
<td>05-07-2010</td> |15-11-2011|Expect assembled boards by mid- December January.|
<td>PCB layout review held.</td> |22-02-2012|Ten assembled boards received. Needs patch on power plane. JTAG, VME and FPGA config work.|
</tr> |30-09-2013|Will produce 20 boards.|
<tr class="even"> |12-02-2015|Obsolete project. Replaced by [VFC-HD](https://www.ohwr.org/vfc-hd/wikis/Description).|
<td>09-08-2010</td>
<td>PCB layout good for production.</td>
</tr>
<tr class="odd">
<td>01-09-2010</td>
<td>Simulation started. Many troubles getting connectivity files out of schematics. Redo by hand.</td>
</tr>
<tr class="even">
<td>15-09-2010</td>
<td>PCB being produced at CERN. Expect assembled boards by mid October.</td>
</tr>
<tr class="odd">
<td>06-10-2010</td>
<td>Two PCB's being assembled. A third one will come later.</td>
</tr>
<tr class="even">
<td>15-10-2010</td>
<td>Problem with solder mask for 0402 capacitors under BGA detected. PCB specification will be changed.</td>
</tr>
<tr class="odd">
<td>19-10-2010</td>
<td>1st prototype received, waiting for the front panel.</td>
</tr>
<tr class="even">
<td>08-11-2010</td>
<td>1st prototype powered: 3 DC/DC are not working.</td>
</tr>
<tr class="odd">
<td>09-11-2010</td>
<td>2nd and 3rd prototype received: one powered and no issues on the PS this time</td>
</tr>
<tr class="even">
<td>17-12-2010</td>
<td>Test code loaded in the System FPGA and PROM programmed. JTAG and PROM loading are working. VME access OK.</td>
</tr>
<tr class="odd">
<td>11-04-2011</td>
<td>Ten additional boards produced. Two reworked and work, but have JTAG issues. Eight still need rework.</td>
</tr>
<tr class="even">
<td>11-04-2011</td>
<td>Modifications to layout required. Can start in two to three weeks time.</td>
</tr>
<tr class="odd">
<td>07-06-2011</td>
<td>Start of <em>sprint</em> to debug the hardware design. 4 engineers intensively working on it, following the <em>scrum methodology</em>.</td>
</tr>
<tr class="even">
<td>24-06-2011</td>
<td>End of <em>sprint</em> to debug hardware design. Uncovered 18 Issues. DDR3 memory and DDS not debugged yet.</td>
</tr>
<tr class="odd">
<td>10-08-2011</td>
<td>New version of schematics ready.</td>
</tr>
<tr class="even">
<td>16-08-2011</td>
<td>Schematics design review held <a href="review16082011" class="uri">review16082011</a>. The design office will layout from 24 August on.</td>
</tr>
<tr class="odd">
<td>13-09-2011</td>
<td>Schematics still being updated. The design office will layout from 19 September on.</td>
</tr>
<tr class="even">
<td>06-10-2011</td>
<td>V2 layout ready. Needs schematics and PCB review.</td>
</tr>
<tr class="odd">
<td>18-10-2011</td>
<td>V2 schematics and PCB review held.</td>
</tr>
<tr class="even">
<td>25-10-2011</td>
<td>Will produce 20 PCBs. First only 10 will be assembled.</td>
</tr>
<tr class="odd">
<td>15-11-2011</td>
<td>Expect assembled boards by mid- <del>December</del> January.</td>
</tr>
<tr class="even">
<td>22-02-2012</td>
<td>Ten assembled boards received. Needs patch on power plane. JTAG, VME and FPGA config work.</td>
</tr>
<tr class="odd">
<td>30-09-2013</td>
<td>Will produce 20 boards.</td>
</tr>
<tr class="even">
<td>12-02-2015</td>
<td>Obsolete project. Replaced by [VFC-HD](https://www.ohwr.org/vfc-hd/wikis/Description).</td>
</tr>
</tbody>
</table>
----- -----
...@@ -203,4 +111,4 @@ Andrea Boccardi, Erik van der Bij - 12 February 2015 ...@@ -203,4 +111,4 @@ Andrea Boccardi, Erik van der Bij - 12 February 2015
### Files ### Files
* [VFC_conns.jpg](/uploads/475af7589a0519125edf7e59ea0c78d1/VFC_conns.jpg) * [VFC_conns.jpg](/uploads/475af7589a0519125edf7e59ea0c78d1/VFC_conns.jpg)
* [VFC_picture.jpg](/uploads/5ae72a7e2e0414ee54edb2be3e185cf9/VFC_picture.jpg) * [VFC_picture.jpg](/uploads/5ae72a7e2e0414ee54edb2be3e185cf9/VFC_picture.jpg)
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