| ... | ... | @@ -70,130 +70,38 @@ VFC](users) |
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## Status
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>03-08-2009</td>
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<td><a href="https://www.ohwr.org/project/fmc-vme-carrier/repository/entry/trunk/documentation/specifications/VFC_FunctionalSpecifications.pdf">Functional specification</a> written.</td>
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</tr>
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<tr class="odd">
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<td>24-03-2010</td>
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<td>PCB layout started</td>
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</tr>
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<tr class="even">
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<td>10-05-2010</td>
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<td>Vadj fixed to 2.5V for FMC slot 2 to solve problems with bank power supplies.</td>
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</tr>
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<tr class="odd">
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<td>11-05-2010</td>
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<td>All active components ordered.</td>
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</tr>
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<tr class="even">
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<td>23-06-2010</td>
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<td>Layout files received and being reviewed.</td>
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</tr>
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<tr class="odd">
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<td>05-07-2010</td>
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<td>PCB layout review held.</td>
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</tr>
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<tr class="even">
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<td>09-08-2010</td>
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<td>PCB layout good for production.</td>
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</tr>
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<tr class="odd">
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<td>01-09-2010</td>
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<td>Simulation started. Many troubles getting connectivity files out of schematics. Redo by hand.</td>
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</tr>
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<tr class="even">
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<td>15-09-2010</td>
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<td>PCB being produced at CERN. Expect assembled boards by mid October.</td>
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</tr>
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<tr class="odd">
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<td>06-10-2010</td>
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<td>Two PCB's being assembled. A third one will come later.</td>
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</tr>
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<tr class="even">
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<td>15-10-2010</td>
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<td>Problem with solder mask for 0402 capacitors under BGA detected. PCB specification will be changed.</td>
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</tr>
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<tr class="odd">
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<td>19-10-2010</td>
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<td>1st prototype received, waiting for the front panel.</td>
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</tr>
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<tr class="even">
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<td>08-11-2010</td>
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<td>1st prototype powered: 3 DC/DC are not working.</td>
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</tr>
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<tr class="odd">
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<td>09-11-2010</td>
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<td>2nd and 3rd prototype received: one powered and no issues on the PS this time</td>
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</tr>
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<tr class="even">
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<td>17-12-2010</td>
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<td>Test code loaded in the System FPGA and PROM programmed. JTAG and PROM loading are working. VME access OK.</td>
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</tr>
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<tr class="odd">
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<td>11-04-2011</td>
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<td>Ten additional boards produced. Two reworked and work, but have JTAG issues. Eight still need rework.</td>
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</tr>
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<tr class="even">
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<td>11-04-2011</td>
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<td>Modifications to layout required. Can start in two to three weeks time.</td>
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</tr>
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<tr class="odd">
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<td>07-06-2011</td>
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<td>Start of <em>sprint</em> to debug the hardware design. 4 engineers intensively working on it, following the <em>scrum methodology</em>.</td>
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</tr>
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<tr class="even">
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<td>24-06-2011</td>
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<td>End of <em>sprint</em> to debug hardware design. Uncovered 18 Issues. DDR3 memory and DDS not debugged yet.</td>
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</tr>
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<tr class="odd">
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<td>10-08-2011</td>
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<td>New version of schematics ready.</td>
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</tr>
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<tr class="even">
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<td>16-08-2011</td>
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<td>Schematics design review held <a href="review16082011" class="uri">review16082011</a>. The design office will layout from 24 August on.</td>
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</tr>
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<tr class="odd">
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<td>13-09-2011</td>
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<td>Schematics still being updated. The design office will layout from 19 September on.</td>
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</tr>
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<tr class="even">
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<td>06-10-2011</td>
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<td>V2 layout ready. Needs schematics and PCB review.</td>
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</tr>
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<tr class="odd">
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<td>18-10-2011</td>
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<td>V2 schematics and PCB review held.</td>
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</tr>
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<tr class="even">
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<td>25-10-2011</td>
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<td>Will produce 20 PCBs. First only 10 will be assembled.</td>
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</tr>
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<tr class="odd">
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<td>15-11-2011</td>
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<td>Expect assembled boards by mid- <del>December</del> January.</td>
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</tr>
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<tr class="even">
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<td>22-02-2012</td>
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<td>Ten assembled boards received. Needs patch on power plane. JTAG, VME and FPGA config work.</td>
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</tr>
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<tr class="odd">
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<td>30-09-2013</td>
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<td>Will produce 20 boards.</td>
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</tr>
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<tr class="even">
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<td>12-02-2015</td>
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<td>Obsolete project. Replaced by [VFC-HD](https://www.ohwr.org/vfc-hd/wikis/Description).</td>
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</tr>
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</tbody>
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|
|
</table>
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|**Date**|**Event**|
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|
|
|
|----|----|
|
|
|
|
|03-08-2009|[Functional specification](https://www.ohwr.org/project/fmc-vme-carrier/repository/entry/trunk/documentation/specifications/VFC_FunctionalSpecifications.pdf) written.|
|
|
|
|
|24-03-2010|PCB layout started|
|
|
|
|
|10-05-2010|Vadj fixed to 2.5V for FMC slot 2 to solve problems with bank power supplies.|
|
|
|
|
|11-05-2010|All active components ordered.|
|
|
|
|
|23-06-2010|Layout files received and being reviewed.|
|
|
|
|
|05-07-2010|PCB layout review held.|
|
|
|
|
|09-08-2010|PCB layout good for production.|
|
|
|
|
|01-09-2010|Simulation started. Many troubles getting connectivity files out of schematics. Redo by hand.|
|
|
|
|
|15-09-2010|PCB being produced at CERN. Expect assembled boards by mid October.|
|
|
|
|
|06-10-2010|Two PCB's being assembled. A third one will come later.|
|
|
|
|
|15-10-2010|Problem with solder mask for 0402 capacitors under BGA detected. PCB specification will be changed.|
|
|
|
|
|19-10-2010|1st prototype received, waiting for the front panel.|
|
|
|
|
|08-11-2010|1st prototype powered: 3 DC/DC are not working.|
|
|
|
|
|09-11-2010|2nd and 3rd prototype received: one powered and no issues on the PS this time|
|
|
|
|
|17-12-2010|Test code loaded in the System FPGA and PROM programmed. JTAG and PROM loading are working. VME access OK.|
|
|
|
|
|11-04-2011|Ten additional boards produced. Two reworked and work, but have JTAG issues. Eight still need rework.|
|
|
|
|
|11-04-2011|Modifications to layout required. Can start in two to three weeks time.|
|
|
|
|
|07-06-2011|Start of sprint to debug the hardware design. 4 engineers intensively working on it, following the scrum methodology.|
|
|
|
|
|24-06-2011|End of sprint to debug hardware design. Uncovered 18 Issues. DDR3 memory and DDS not debugged yet.|
|
|
|
|
|10-08-2011|New version of schematics ready.|
|
|
|
|
|16-08-2011|Schematics design review held [review16082011](review16082011). The design office will layout from 24 August on.|
|
|
|
|
|13-09-2011|Schematics still being updated. The design office will layout from 19 September on.|
|
|
|
|
|06-10-2011|V2 layout ready. Needs schematics and PCB review.|
|
|
|
|
|18-10-2011|V2 schematics and PCB review held.|
|
|
|
|
|25-10-2011|Will produce 20 PCBs. First only 10 will be assembled.|
|
|
|
|
|15-11-2011|Expect assembled boards by mid- December January.|
|
|
|
|
|22-02-2012|Ten assembled boards received. Needs patch on power plane. JTAG, VME and FPGA config work.|
|
|
|
|
|30-09-2013|Will produce 20 boards.|
|
|
|
|
|12-02-2015|Obsolete project. Replaced by [VFC-HD](https://www.ohwr.org/vfc-hd/wikis/Description).|
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|
|
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-----
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| ... | ... | |
