| ... | @@ -17,8 +17,12 @@ |
... | @@ -17,8 +17,12 @@ |
|
|
- 1 Direct Digital Synthesizer (DDS)
|
|
- 1 Direct Digital Synthesizer (DDS)
|
|
|
- 3 Phase Locked Loop (PLL) chips for clock cleaning and
|
|
- 3 Phase Locked Loop (PLL) chips for clock cleaning and
|
|
|
redistribution to the FPGAs and the pluggable modules
|
|
redistribution to the FPGAs and the pluggable modules
|
|
|
- 2 completely independent 72Mbit ZBT SRAMS
|
|
- Large amount of on board mamory
|
|
|
- A 2Gbit DDR3
|
|
- 2 completely independent 72Mbit ZBT SRAMS
|
|
|
|
- A 2Gbit DDR3
|
|
|
|
- 2 SPI 128Mbit flash proms for multiboot S-FPGA powerup
|
|
|
|
configuration, storage of the A-FPGA firmware or of critical
|
|
|
|
data
|
|
|
- Front panel connectivity
|
|
- Front panel connectivity
|
|
|
- 2 Small Formfactor Pluggable (SFP)
|
|
- 2 Small Formfactor Pluggable (SFP)
|
|
|
- 4 lemos configurable in all possible input/output combinations
|
|
- 4 lemos configurable in all possible input/output combinations
|
| ... | | ... | |
