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## 02-02-2012: V2 design ready
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_added by Erik van der Bij on 2012-02-02 16:23:55.103167_
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Based on the experience with the V1 prototype, nine
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[Issues](https://www.ohwr.org/project/fmc-tdc/issues) were found.
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Corrections have been made to the schematics and PCB layout and these
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will be reviewed on 7 February. After this CERN's design office will
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generate the final production files.
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The firmware VHDL code is under thorough review and production test
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software has to be written. This work should be ready by the end of the
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summer.
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## 30-05-2011: 3 prototypes assembled
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_added by Erik van der Bij on 2011-05-30 13:35:49.879354_
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Three prototypes of the Time to Digital converter have been built. We
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made a start of the VHDL coding for use on the SPEC PCI Express FMC
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carrier.
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## 18-03-2011: Schematics design review held
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_added by Erik van der Bij on 2011-03-18 14:58:49.834557_
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After a first global schematics review in the week before, a second
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schematics design review was held with five engineers who found a few
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details that will improve the functioning and the documentation of the
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schematics. The PCB layout will likely start in a week's time.
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