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# FMC Time to Digital Converter: FMC TDC 1ns 5cha
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tdc\_v1\_before\_review
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# System specifications
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- 5 inputs, TTL with software selectable 50 Ohm termination.
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-----
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# Project documents
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- **Official production documentation (schematics, PCB, etc.):**
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[EDMS: EDA-02290](https://edms.cern.ch/nav/EDA-02290)
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<!-- end list -->
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- LHC Equipment name:
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<!-- end list -->
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- [Literature](Literature)
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-----
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# Literature
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- [A 17ps Time-to-Digital Converter Implemented in 65nm FPGA
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<td>18-03-2011</td>
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<td>Second schematics design review held.</td>
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</tr>
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<tr class="even">
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<td>05-04-2011</td>
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<td>First layout made. Will be reviewed.</td>
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</tr>
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</tbody>
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</table>
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-----
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Javier Serrano, Erik van der Bij - 18 March 2011
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Javier Serrano, Erik van der Bij - 7 April 2011
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