... | ... | @@ -18,75 +18,31 @@ views](https://www.ohwr.org/project/fmc-tdc/wikis/Documents/Images) )* |
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## Specifications
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<table>
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<tbody>
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<tr class="odd">
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<td>Input Channels</td>
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<td><strong>5 channels TTL</strong> with software selectable 50 Ohm termination (<a href="http://www.ti.com/lit/ds/symlink/cdclvc1102.pdf)">CDCLVC1102PW</a><br />
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Inputs are protected against +15V pulses with a pulse width of at least 10us at 50Hz</td>
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</tr>
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<tr class="even">
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<td>Channels enable</td>
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<td>Software controlled switch that <strong>enables/disables</strong> all 5 channels</td>
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</tr>
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<tr class="odd">
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<td>Timestamps buffer</td>
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<td><strong>Circular buffer</strong> that keeps the last <strong>128 pulses</strong> (256 rising and falling edges);<br />
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programmable interrupts implemented based on the number of accumulated timestamps or the amount of elapsed time</td>
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</tr>
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<tr class="even">
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<td></td>
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</tr>
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<tr class="odd">
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<td>Timestamps precision (deviation)</td>
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<td><strong>± 700 ps</strong><br />
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Outliers of ±4 ns are observed at the expected frequency of ~ 1 outlier/10M measurements.<br />
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More information at [Board Performance documents](https://www.ohwr.org/project/fmc-tdc/wikis/board-performance).</td>
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</tr>
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<tr class="even">
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<td>Timebase accuracy</td>
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<td>With White Rabbit: *< 1ns*<br />
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Without White Rabbit: <strong>± 4 ppm</strong> from a local TCXO on the FMC card</td>
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</tr>
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<tr class="odd">
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<td>Maximum input pulse rate</td>
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<td><strong>31.25 MHz</strong> from all 5 channels</td>
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</tr>
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<tr class="even">
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<td></td>
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</tr>
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<tr class="odd">
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<td>Timestamps</td>
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<td>Timestamps apply to both <strong>rising and falling edges</strong> of incoming pulses;<br />
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on the software level the falling edges are only used for the calculation of the pulse width, ignoring pulses < 100 ns;<br />
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With White Rabbit, the TDC offers <strong>absolute timestamping</strong> and timestamps from different boards in the same White Rabbit network can be correlated.<br />
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Without White Rabbit the timestamps from one board need to be always <strong>subtracted</strong> between them, to calculate time differences</td>
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</tr>
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<tr class="even">
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<td>Minimum input pulse width</td>
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<td><strong>100 ns</strong>, narrower pulses are ignored on software level by subtracting a falling edge from the previous rising one</td>
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</tr>
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<tr class="odd">
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<td>ACAM mode</td>
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<td><strong>I-mode</strong>, 81ps resolution, +/- 500ps precision (6σ)</td>
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</tr>
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<tr class="even">
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<td></td>
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</tr>
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<tr class="odd">
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<td>Connectors</td>
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<td><strong>LEMO</strong> 00</td>
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</tr>
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<tr class="even">
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<td>FMC connector</td>
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<td>Low Pin Count</td>
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</tr>
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<tr class="odd">
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<td>PCB</td>
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<td>6 layers</td>
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</tr>
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</tbody>
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</table>
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|Input Channels|**5 channels TTL** with software selectable 50 Ohm termination ([CDCLVC1102PW](http://www.ti.com/lit/ds/symlink/cdclvc1102.pdf))
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Inputs are protected against +15V pulses with a pulse width of at least 10us at 50Hz|
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|----|----|
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|Channels enable|Software controlled switch that **enables/disables** all 5 channels|
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|Timestamps buffer|**Circular buffer** that keeps the last **128 pulses** (256 rising and falling edges);
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programmable interrupts implemented based on the number of accumulated timestamps or the amount of elapsed time|
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||
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|Timestamps precision (deviation)|**± 700 ps**
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Outliers of ±4 ns are observed at the expected frequency of ~ 1 outlier/10M measurements.
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More information at [Board Performance documents](https://www.ohwr.org/project/fmc-tdc/wikis/board-performance).|
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|Timebase accuracy|With White Rabbit: *< 1ns*
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Without White Rabbit: **± 4 ppm** from a local TCXO on the FMC card|
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|Maximum input pulse rate|**31.25 MHz** from all 5 channels|
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||
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|Timestamps|Timestamps apply to both **rising and falling edges** of incoming pulses;
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on the software level the falling edges are only used for the calculation of the pulse width, ignoring pulses < 100 ns;
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With White Rabbit, the TDC offers **absolute timestamping** and timestamps from different boards in the same White Rabbit network can be correlated.
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Without White Rabbit the timestamps from one board need to be always **subtracted** between them, to calculate time differences|
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|Minimum input pulse width|**100 ns**, narrower pulses are ignored on software level by subtracting a falling edge from the previous rising one|
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|ACAM mode|**I-mode**, 81ps resolution, +/- 500ps precision (6σ)|
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||
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|Connectors|**LEMO** 00|
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|FMC connector|Low Pin Count|
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|PCB|6 layers|
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-----
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... | ... | @@ -95,226 +51,79 @@ Without White Rabbit the timestamps from one board need to be always <strong>sub |
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The FMC TDC development consists of the following sub-projects; each
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sub-project has its corresponding release.
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Link to Sub-project</strong></td>
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<td><strong>Description</strong></td>
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<td><strong>Release</strong></td>
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</tr>
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<tr class="even">
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<td>[Hardware](https://www.ohwr.org/project/fmc-tdc-1ns-5cha-hw/wiki)</td>
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<td>Design of the TDC mezzanine board</td>
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<td>[Hardware release EDA-02290](https://edms.cern.ch/nav/EDA-02290)</td>
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</tr>
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<tr class="odd">
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<td>[Gateware](https://www.ohwr.org/project/fmc-tdc-1ns-5cha-gw/wiki)</td>
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<td>Associated gateware housed in the FPGA of the carrier</td>
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<td>[Gateware release](https://www.ohwr.org/project/fmc-tdc-1ns-5cha-gw/wikis/Gateware_release)</td>
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</tr>
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<tr class="even">
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<td>[Software](https://www.ohwr.org/project/fmc-tdc-sw/wiki)</td>
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<td>Dedicated Linux software support</td>
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<td></td>
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</tr>
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<tr class="odd">
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<td>[Testing](https://www.ohwr.org/project/fmc-tdc-1ns-5cha-tst/wiki)</td>
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<td>Long runs on the whole of the application (hw, gw, sw) and dedicated Production Test Suite and Calibration</td>
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<td>PTS release</td>
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</tr>
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</tbody>
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</table>
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|**Link to Sub-project**|**Description**|**Release**|
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|----|----|----|
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|[Hardware](https://www.ohwr.org/project/fmc-tdc-1ns-5cha-hw/wiki)|Design of the TDC mezzanine board|[Hardware release EDA-02290](https://edms.cern.ch/nav/EDA-02290)|
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|[Gateware](https://www.ohwr.org/project/fmc-tdc-1ns-5cha-gw/wiki)|Associated gateware housed in the FPGA of the carrier|[Gateware release](https://www.ohwr.org/project/fmc-tdc-1ns-5cha-gw/wikis/Gateware_release)|
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|[Software](https://www.ohwr.org/project/fmc-tdc-sw/wiki)|Dedicated Linux software support||
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|[Testing](https://www.ohwr.org/project/fmc-tdc-1ns-5cha-tst/wiki)|Long runs on the whole of the application (hw, gw, sw) and dedicated Production Test Suite and Calibration|PTS release|
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-----
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## Project documents
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Link to document</strong></td>
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<td><strong>Description</strong></td>
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</tr>
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<tr class="even">
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<td>[FMC TDC User’s Manual](https://www.ohwr.org/project/fmc-tdc/uploads/5cdb53a7de354c90b86f992636f99485/fmc-tdc.pdf)</td>
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<td>FMC TDC 1ns-5cha hardware and software manual - July 2013 (in [-SW project](https://www.ohwr.org/project/fmc-tdc-sw/wikis/documents))</td>
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</tr>
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<tr class="odd">
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<td>[Board Performance](Board-Performance)</td>
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<td>On precision and performance over time</td>
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</tr>
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<tr class="even">
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<td>[Literature](Literature)</td>
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<td>Relevant literature about Time to Digital conversion</td>
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</tr>
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<tr class="odd">
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<td>[Users](Users)</td>
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<td>Known users inside and outside CERN</td>
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</tr>
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<tr class="even">
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<td>[CERN specific information](CERN)</td>
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<td>-</td>
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</tr>
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</tbody>
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</table>
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|**Link to document**|**Description**|
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|----|----|
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|[FMC TDC User’s Manual](https://www.ohwr.org/project/fmc-tdc/uploads/5cdb53a7de354c90b86f992636f99485/fmc-tdc.pdf)|FMC TDC 1ns-5cha hardware and software manual - July 2013 (in [-SW project](https://www.ohwr.org/project/fmc-tdc-sw/wikis/documents))|
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|[Board Performance](Board-Performance)|On precision and performance over time|
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|[Literature](Literature)|Relevant literature about Time to Digital conversion|
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|[Users](Users)|Known users inside and outside CERN|
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|[CERN specific information](CERN)|-|
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|
-----
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## Contacts
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>General Questions</strong></td>
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<td><a href="mailto:Erik.van.der.Bij@cern.ch">Erik van der Bij</a>, <a href="mailto:EGousiou@cern.ch">Eva Gousiou</a> at CERN</td>
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</tr>
|
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|
<tr class="even">
|
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<td><strong>Commercial producers</strong></td>
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<td><a href="http://sevensols.com/index.php/fmc-tdc/">FMC TDC</a>, <a href="http://www.sevensols.com/">Seven Solutions</a>, Spain<br />
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|
|
<a href="https://www.janztec.com/en/embedded-pc/vmebus/fmc-tdc/">BO-FMC-02290: FMC TDC 1ns</a>, <a href="http://www.janztec.com/en/">Janz Tec AG</a>, Germany</td>
|
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</tr>
|
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|
</tbody>
|
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|
</table>
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|**General Questions**|[Erik van der Bij](mailto:Erik.van.der.Bij@cern.ch), [Eva Gousiou](mailto:EGousiou@cern.ch) at CERN|
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|----|----|
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|**Commercial producers**|[FMC TDC](http://sevensols.com/index.php/fmc-tdc/), [Seven Solutions](http://www.sevensols.com/), Spain
|
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[BO-FMC-02290: FMC TDC 1ns](https://www.janztec.com/en/embedded-pc/vmebus/fmc-tdc/), [Janz Tec AG](http://www.janztec.com/en/), Germany|
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|
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|
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|
-----
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## Project Status
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>06-12-2010</td>
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<td>Project start</td>
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</tr>
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<tr class="odd">
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<td>14-12-2010</td>
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<td>First specification available for comments</td>
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</tr>
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<tr class="even">
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<td>09-03-2011</td>
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<td>First schematic available. (need to replace LEDs)</td>
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</tr>
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<tr class="odd">
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<td>18-03-2011</td>
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<td>Second schematics design review held</td>
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</tr>
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<tr class="even">
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<td>08-04-2011</td>
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<td>First layout made. Review made, needs moving of components ([check review#1](https://www.ohwr.org/documents/338))</td>
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</tr>
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<tr class="odd">
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<td>11-04-2011</td>
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<td>Layout being modified. Planning: 3 assembled prototypes by 16 May</td>
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</tr>
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<tr class="even">
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<td>19-04-2011</td>
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<td>New layout received. Design review on 20-04-2011</td>
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</tr>
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<tr class="odd">
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<td>20-04-2011</td>
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<td>Review held (<a href="https://www.ohwr.org/documents/338">check review#2</a> ); layout office modifies the design</td>
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</tr>
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<tr class="even">
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<td>29-04-2011</td>
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<td>Layout office finalized the design</td>
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</tr>
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<tr class="odd">
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<td>30-05-2011</td>
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<td>Three prototypes ready</td>
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</tr>
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<tr class="even">
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<td>01-06-2011</td>
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<td>Start of writing firmware</td>
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</tr>
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<tr class="odd">
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<td>05-08-2011</td>
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<td>Design specification review held (<a href="https://www.ohwr.org/project/fmc-tdc-1ns-5cha-gw/tree/fea36da15faebc79c4de4406472e80506b880969/hdl/spec/src/code_review_08-11-2011">check review</a> )</td>
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</tr>
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<tr class="even">
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<td>08-08-2011</td>
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<td>Basic functionality OK. Several issues found that need a new PCB layout</td>
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</tr>
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<tr class="odd">
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<td>16-12-2011</td>
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<td>New PCB layout made. Production files will be generated</td>
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</tr>
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<tr class="even">
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<td>02-02-2012</td>
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<td>V2 schematics and PCB made. Will be reviewed on 7 February. Foresee production 8 boards for 23 March.</td>
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</tr>
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<tr class="odd">
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<td>07-02-2012</td>
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<td>Schematics reviewed (<a href="https://www.ohwr.org/documents/338">check review#3</a> ); improved schematics ready by 21-02-2012 for new review</td>
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</tr>
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<tr class="even">
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<td>30-05-2012</td>
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<td>V2 boards received</td>
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</tr>
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<tr class="odd">
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<td>30-08-2012</td>
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<td>V3 schematics and PCB being made; input circuit modified</td>
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</tr>
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<tr class="even">
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<td>23-10-2012</td>
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<td>V3 schematics and PCB ready</td>
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</tr>
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<tr class="odd">
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<td>15-11-2012</td>
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<td>Ordered 60 V3 boards: 10 for delivery by <del>begin March</del> end April 2013, 50 by begin May 2013 ([check order](https://edh.cern.ch/Document/SupplyChain/DAI/5108860))</td>
|
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|
</tr>
|
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|
<tr class="even">
|
|
|
<td>04-12-2012</td>
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|
|
<td>Feedback on design received. Can use same PCB. Other changes may be handled in a V4</td>
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|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>25-03-2013</td>
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|
|
<td>Will make V3-1 design (only change of BOM) to handle [five issues](https://www.ohwr.org/project/fmc-tdc/versions/15)</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>08-04-2013</td>
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|
|
<td>Working on: correcting two firmware bugs, writing documentation, writing software to test firmware</td>
|
|
|
</tr>
|
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<tr class="odd">
|
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|
<td>26-04-2013</td>
|
|
|
<td>No known firmware bugs left. Writing calibration test program</td>
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|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>06-05-2013</td>
|
|
|
<td>V3-1 design ready (only change of BOM) to handle [five issues](https://www.ohwr.org/project/fmc-tdc/versions/15)</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>13-05-2013</td>
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|
|
<td>CERN received 9 pre-series V3-1 boards</td>
|
|
|
</tr>
|
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|
<tr class="even">
|
|
|
<td>22-05-2013</td>
|
|
|
<td>CERN accepted quality of pre-series V3-1 boards;<br />
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|
|
production of 50 series (original foreseen for delivery in May 2013) started</td>
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</tr>
|
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<tr class="odd">
|
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<td>09-08-2013</td>
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<td>51 V3-1 boards received</td>
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</tr>
|
|
|
<tr class="even">
|
|
|
<td>20-06-2014</td>
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|
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<td>Added White Rabbit support for SVEC and SPEC</td>
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</tr>
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<tr class="odd">
|
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<td>04-07-2014</td>
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<td>Ordered 60 V3-1 boards: 20 for delivery by end October 2014, 40 by begin January 2015 ([check order](https://edh.cern.ch/Document/SupplyChain/DAI/5718677))</td>
|
|
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</tr>
|
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<tr class="even">
|
|
|
<td>10-07-2014</td>
|
|
|
<td>Project split into hw, gw, sw sub-projects</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|**Date**|**Event**|
|
|
|
|----|----|
|
|
|
|06-12-2010|Project start|
|
|
|
|14-12-2010|First specification available for comments|
|
|
|
|09-03-2011|First schematic available. (need to replace LEDs)|
|
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|18-03-2011|Second schematics design review held|
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|08-04-2011|First layout made. Review made, needs moving of components ([check review#1](https://www.ohwr.org/documents/338))|
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|11-04-2011|Layout being modified. Planning: 3 assembled prototypes by 16 May|
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|19-04-2011|New layout received. Design review on 20-04-2011|
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|20-04-2011|Review held ([check review#2](https://www.ohwr.org/documents/338) ); layout office modifies the design|
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|29-04-2011|Layout office finalized the design|
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|30-05-2011|Three prototypes ready|
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|01-06-2011|Start of writing firmware|
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|05-08-2011|Design specification review held ([check review](https://www.ohwr.org/project/fmc-tdc-1ns-5cha-gw/tree/fea36da15faebc79c4de4406472e80506b880969/hdl/spec/src/code_review_08-11-2011) )|
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|08-08-2011|Basic functionality OK. Several issues found that need a new PCB layout|
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|16-12-2011|New PCB layout made. Production files will be generated|
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|02-02-2012|V2 schematics and PCB made. Will be reviewed on 7 February. Foresee production 8 boards for 23 March.|
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|07-02-2012|Schematics reviewed ([check review#3](https://www.ohwr.org/documents/338) ); improved schematics ready by 21-02-2012 for new review|
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|30-05-2012|V2 boards received|
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|30-08-2012|V3 schematics and PCB being made; input circuit modified|
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|23-10-2012|V3 schematics and PCB ready|
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|15-11-2012|Ordered 60 V3 boards: 10 for delivery by begin March end April 2013, 50 by begin May 2013 ([check order](https://edh.cern.ch/Document/SupplyChain/DAI/5108860))|
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|04-12-2012|Feedback on design received. Can use same PCB. Other changes may be handled in a V4|
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|25-03-2013|Will make V3-1 design (only change of BOM) to handle [five issues](https://www.ohwr.org/project/fmc-tdc/versions/15)|
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|08-04-2013|Working on: correcting two firmware bugs, writing documentation, writing software to test firmware|
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|26-04-2013|No known firmware bugs left. Writing calibration test program|
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|06-05-2013|V3-1 design ready (only change of BOM) to handle [five issues](https://www.ohwr.org/project/fmc-tdc/versions/15)|
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|13-05-2013|CERN received 9 pre-series V3-1 boards|
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|22-05-2013|CERN accepted quality of pre-series V3-1 boards;
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production of 50 series (original foreseen for delivery in May 2013) started|
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|09-08-2013|51 V3-1 boards received|
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|20-06-2014|Added White Rabbit support for SVEC and SPEC|
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|04-07-2014|Ordered 60 V3-1 boards: 20 for delivery by end October 2014, 40 by begin January 2015 ([check order](https://edh.cern.ch/Document/SupplyChain/DAI/5718677))|
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|10-07-2014|Project split into hw, gw, sw sub-projects|
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-----
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Eva Gousiou | Javier Serrano | Erik van der Bij | 26 September 2018
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