... | @@ -87,7 +87,8 @@ guide](https://www.ohwr.org/3017) |
... | @@ -87,7 +87,8 @@ guide](https://www.ohwr.org/3017) |
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# Release
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# Release
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The gateware is housed on the FPGA of the carrier. The architecture
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The gateware is housed on the FPGA of the carrier. The architecture
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principles are the same between the two carriers.
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principles are the same between the two carriers; however there are some
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top level differences.
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For the binaries, memory maps, gateware architecture and VHDL sources,
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For the binaries, memory maps, gateware architecture and VHDL sources,
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follow the corresponding links:
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follow the corresponding links:
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... | @@ -110,7 +111,24 @@ follow the corresponding links: |
... | @@ -110,7 +111,24 @@ follow the corresponding links: |
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# Documents
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# Documents
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- Gateware architecture for SPEC and SVEC carrier
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<table>
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- Memory map for SPEC carrier
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<tbody>
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- Memory map for SVEC carrier
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<tr class="odd">
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<td><strong>Document</strong></td>
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<td><strong>Description</strong></td>
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</tr>
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<tr class="even">
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<td>[Gateware guide for SPEC and SVEC carrier](https://www.ohwr.org/3017)</td>
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<td>in depth description of the gateware architecture</td>
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</tr>
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<tr class="odd">
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<td>[Memory map for SPEC carrier](https://www.ohwr.org/3021)</td>
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<td>short document on the register mapping and establishment of basic communication on a SPEC carrier</td>
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</tr>
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<tr class="even">
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<td>[Memory map for SVEC carrier](https://www.ohwr.org/3020)</td>
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<td>short document on the register mapping and establishment of basic communication on a SVEC carrier</td>
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</tr>
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</tbody>
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</table>
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