... | @@ -26,7 +26,7 @@ As both figures show the design is highly **modular** and the |
... | @@ -26,7 +26,7 @@ As both figures show the design is highly **modular** and the |
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communication of all the modules with the PCIe interface is based on
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communication of all the modules with the PCIe interface is based on
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WISHBONE.
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WISHBONE.
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![](/uploads/b7d769b5c446a385ce512622f3cd1aa9/gw_architecture2.jpg)
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![](https://ohwr.org/project/fmc-tdc-1ns-5cha-gw/uploads/b7d769b5c446a385ce512622f3cd1aa9/gw_architecture2.jpg)
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*Figure 1: SPEC TDC gateware architecture***
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*Figure 1: SPEC TDC gateware architecture***
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The main parts of the design, as shown in Figure 1 are:
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The main parts of the design, as shown in Figure 1 are:
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... | @@ -64,7 +64,7 @@ it is then putting them in a user-convenient format and finally it is |
... | @@ -64,7 +64,7 @@ it is then putting them in a user-convenient format and finally it is |
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making them **available to the PCIe
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making them **available to the PCIe
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interface**.
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interface**.
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![](/uploads/ae71bb5a21c9c5dc54e196963f8667e1/FMC_TDC_mezzanine_architecture2.jpg)
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![](https://ohwr.org/project/fmc-tdc-1ns-5cha-gw/uploads/ae71bb5a21c9c5dc54e196963f8667e1/FMC_TDC_mezzanine_architecture2.jpg)
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*Figure 2: FMC TDC mezzanine gateware architecture***
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*Figure 2: FMC TDC mezzanine gateware architecture***
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As of June 2014 the TDC design has been extended to include [White
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As of June 2014 the TDC design has been extended to include [White
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... | @@ -79,7 +79,7 @@ The **timebase accuracy** is reduced to \< 1 ns, in comparison to the |
... | @@ -79,7 +79,7 @@ The **timebase accuracy** is reduced to \< 1 ns, in comparison to the |
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boards in the same White Rabbit network can now be compared to each
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boards in the same White Rabbit network can now be compared to each
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other.
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other.
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![](/uploads/29494c7aa8214987dd2b0b05e8091b12/gw_architecture_wrabbit2.jpg)
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![](https://ohwr.org/project/fmc-tdc-1ns-5cha-gw/uploads/29494c7aa8214987dd2b0b05e8091b12/gw_architecture_wrabbit2.jpg)
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*Figure 3: FMC TDC mezzanine gateware architecture with White Rabbit
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*Figure 3: FMC TDC mezzanine gateware architecture with White Rabbit
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support***
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support***
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... | @@ -104,9 +104,9 @@ follow the corresponding links: |
... | @@ -104,9 +104,9 @@ follow the corresponding links: |
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|**Document**|**Description**|
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|**Document**|**Description**|
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|----|----|
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|----|----|
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|[Gateware Guide](https://www.ohwr.org/project/fmc-tdc-1ns-5cha-gw/uploads/923dece7ba14a55e5ee338ffa7b13fb8/TDC_gw_guide_release_7_0.pdf)|in depth description of the gateware architecture for a SPEC and a SVEC carrier|
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|[Gateware Guide](https://ohwr.org/project/fmc-tdc-1ns-5cha-gw/uploads/923dece7ba14a55e5ee338ffa7b13fb8/TDC_gw_guide_release_7_0.pdf)|in depth description of the gateware architecture for a SPEC and a SVEC carrier|
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|[SPEC Memory Map](https://www.ohwr.org/3124)|short document on the register mapping and establishment of basic communication on a SPEC carrier|
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|[SPEC Memory Map](https://www.ohwr.org/3124)|short document on the register mapping and establishment of basic communication on a SPEC carrier|
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|[SVEC Memory Map](https://www.ohwr.org/project/fmc-tdc-1ns-5cha-gw/uploads/be1eb3c3f711a38f3cccf7c8f23c69ff/SVEC_TDC_manual_release_6_0.pdf)|short document on the register mapping and establishment of basic communication on a SVEC carrier|
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|[SVEC Memory Map](https://ohwr.org/project/fmc-tdc-1ns-5cha-gw/uploads/be1eb3c3f711a38f3cccf7c8f23c69ff/SVEC_TDC_manual_release_6_0.pdf)|short document on the register mapping and establishment of basic communication on a SVEC carrier|
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