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# FMC Time to Digital Converter Gateware
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# FMC Time to Digital Converter Gateware
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The Time to Digital Converter mezzanine board FMC TDC 1ns 5cha has 5
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The Time to Digital Converter mezzanine board FMC TDC 1ns 5cha has 5
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input channels. Its purpose is to calculate time differences between
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input channels. Its purpose is to calculate **time differences** between
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pulses arriving to the channels with a precision of ±700 ps. It follows
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pulses arriving to the channels with a precision of ±700 ps.
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the FMC architecture and can be carried by any carrier board like the
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It follows the FMC architecture and can be carried by any carrier board
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[SPEC](www.ohwr.org/project/spec/wiki) or the
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like the [SPEC](www.ohwr.org/project/spec/wiki) or the
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[SVEC](www.ohwr.org/project/svec/wiki). It is using a dedicated
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[SVEC](www.ohwr.org/project/svec/wiki). It is using a dedicated
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time-to-digital converter chip
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time-to-digital converter chip
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[TDC-GPX](http://www.acam.de/fileadmin/Download/pdf/TDC/English/DB_GPX_en.pdf)
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[TDC-GPX](http://www.acam.de/fileadmin/Download/pdf/TDC/English/DB_GPX_en.pdf)
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... | @@ -12,20 +12,22 @@ of the European company ACAM. |
... | @@ -12,20 +12,22 @@ of the European company ACAM. |
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The carrier board, SPEC or SVEC, provides FPGA logic, power supplies,
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The carrier board, SPEC or SVEC, provides FPGA logic, power supplies,
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clocking resources as well as the interface to the PCIe (SPEC) or VME64x
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clocking resources as well as the interface to the PCIe (SPEC) or VME64x
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(SVEC) bus. The TDC mezzanine board houses mainly the five input
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(SVEC) bus.
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channels and the ACAM time-to-digital converter chip. One mezzanine can
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The TDC mezzanine board houses mainly the five input channels and the
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be plugged on the SPEC carrier, whereas up to two mezzanines can be
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ACAM time-to-digital converter chip.
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plugged on the SVEC carrier.
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Figure 1 shows the gateware architecture for the simpler case of the
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Figure 1 shows the gateware architecture for the simpler case of the
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SPEC carrier. Figure 2 zooms into the main module of Figure 1 depicted
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SPEC carrier. Figure 2 zooms into the main module of Figure 1 depicted
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in green. As both figures show the design is highly modular and the
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in green.
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As both figures show the design is highly **modular** and the
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communication of all the modules with the PCIe interface is based on
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communication of all the modules with the PCIe interface is based on
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WISHBONE.
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WISHBONE.
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https://www.ohwr.org/3012
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https://www.ohwr.org/3012
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*Figure 1: SPEC TDC gateware architecture*
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*Figure 1: SPEC TDC gateware architecture*
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The main parts of the design, as shown in Figure 1 are:
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- The **GN4124 core** is the interface to the Gennum GN4124 PCIe
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- The **GN4124 core** is the interface to the Gennum GN4124 PCIe
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bridge chip. The core provides a WISHBONE master where all the other
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bridge chip. The core provides a WISHBONE master where all the other
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FPGA modules can connect to and gain access to the PCIe.
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FPGA modules can connect to and gain access to the PCIe.
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... | @@ -45,19 +47,20 @@ https://www.ohwr.org/3012 |
... | @@ -45,19 +47,20 @@ https://www.ohwr.org/3012 |
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- The vector **interrupt** controller, VIC, is multiplexing different
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- The vector **interrupt** controller, VIC, is multiplexing different
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interrupt lines into one single line to the host.
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interrupt lines into one single line to the host.
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- The **crossbar** is used to map the different slaves in the WISHBONE
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- The **crossbar** is used to map the different slaves in the WISHBONE
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address
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address space.
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space.
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Figure 2 shows the different parts of the **FMC TDC mezzanine module**
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and their connections to the TDC mezzanine board. The heart of this
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module is the **TDC core**, depicted in pink.
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The TDC core is first responsible for **configuring** the ACAM chip. The
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configuration instructions are provided through the PCIe interface.
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Once the ACAM chip is configured, rising edges arriving to any of its
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channels are **time-stamped**. The TDC core is responsible for
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retrieving the timestamps;
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it is then putting them in a user-convenient format and finally it is
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making them **available to the PCIe
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interface**.
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https://www.ohwr.org/3013
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https://www.ohwr.org/3013
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*Figure 2: FMC TDC mezzanine gateware architecture*
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*Figure 2: FMC TDC mezzanine gateware architecture*
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Figure 2 shows the different parts of the FMC TDC mezzanine module and
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their connections to the TDC mezzanine board. The heart of this module
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is the TDC core, depicted in pink. The TDC core is first responsible for
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configuring the ACAM chip. The configuration instructions are provided
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through the PCIe interface. Once the ACAM chip is configured, rising
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edges arriving to any of its channels are time-stamped. The TDC core is
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responsible for retrieving the timestamps; it is then putting them in a
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user-convenient format and finally it is making them available to the
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PCIe interface.
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