... | ... | @@ -10,9 +10,9 @@ time-to-digital converter chip |
|
|
[TDC-GPX](http://www.acam.de/fileadmin/Download/pdf/TDC/English/DB_GPX_en.pdf)
|
|
|
of the European company ACAM.
|
|
|
|
|
|
The carrier board, SPEC or SVEC, provides FPGA logic, power supplies,
|
|
|
clocking resources as well as the interface to the PCIe (SPEC) or VME64x
|
|
|
(SVEC) bus.
|
|
|
The carrier board, SPEC or SVEC, provides **FPGA logic**, power
|
|
|
supplies, clocking resources as well as the interface to the PCIe (SPEC)
|
|
|
or VME64x (SVEC) bus.
|
|
|
The TDC mezzanine board houses mainly the five input channels and the
|
|
|
ACAM time-to-digital converter chip.
|
|
|
|
... | ... | @@ -81,18 +81,36 @@ https://www.ohwr.org/3015 |
|
|
support*
|
|
|
|
|
|
For more information on the FMC TDC gateware design, please consult the
|
|
|
dedicated "gateware
|
|
|
guide:"https://www.ohwr.org/3017"
|
|
|
dedicated [gateware
|
|
|
guide](https://www.ohwr.org/3017)
|
|
|
|
|
|
# Release
|
|
|
|
|
|
The gateware is housed on the FPGA of the carrier. The architecture
|
|
|
principles are the same between the two carriers.
|
|
|
For the binaries, memory maps, gateware architecture and VHDL sources,
|
|
|
follow the corresponding links:
|
|
|
|
|
|
<table>
|
|
|
<tbody>
|
|
|
<tr class="odd">
|
|
|
<td>[Gateware](https://www.ohwr.org/project/fmc-tdc-1ns-5cha-gw/wiki)</td>
|
|
|
<td>Associated gateware housed in the FPGA of the carrier</td>
|
|
|
<td>[Gateware release](gateware-release)</td>
|
|
|
<td><strong>Carrier</strong></td>
|
|
|
<td><strong>Release page</strong></td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>SPEC</td>
|
|
|
<td>[SPEC gateware releases](gateware-release)</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>SVEC</td>
|
|
|
<td>[SVEC gateware releases](gateware-release)</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|
|
|
# Documents
|
|
|
|
|
|
- Gateware architecture for SPEC and SVEC carrier
|
|
|
- Memory map for SPEC carrier
|
|
|
- Memory map for SVEC carrier
|
|
|
|