Project description
This actually not a hardware project, but is there to help you find your way in the FMC standard and shows you which FMC Mezzanines and Carriers are being developed in the context of the Open Hardware project.
OHR developments
FMC Carriers
- PCI Express Carrier with 1 FMC slot. Xilinx Spartan (CERN BE/CO)
- VME FMC Carrier with 2 FMC slots. Xilinx Virtex (CERN BE/BI)
- VME FMC Carrier with 2 FMC slots. Xilinx FPGA and TI DSP (CERN BE/RF)
FMC Mezzanines
Digital I/O
-
16-channel TTL I/O
(CERN BE/CO, M.Cattin) - prototype produced (15/2/10)
- programmable as 8 in/8 out, 16 in or 16 out.
Analog to Digital Converters
Overview of specifications of CERN developments at FMCAdcProjects.
-
FmcAdc100M14b4cha: 100 MSPS, 14 bits, 4
channel (CERN
BE/CO) - being designed
- User: BPM Linac4. To be used on VME carrier (L.Soby, M.Sordet 1st beam end 2010)
- User: OASIS general purpose (Deghaye)
- FmcAdc1/FMC2: 100 MSPS, 2 channel, 14 bit max. with auto calibration - (CERN BE/CO) - cancelled
- FmcAdc2/FMC1: 1 MSPS, 8 channel, 16 bit max. (CERN BE/CO) - design not started
- 128 ksps ADC (CERN TE/EPC, Q. King, G. Ramseier) - under design
- 128 kSPS (50 kHz bandwidth) with an ADS1274 Simultaneous Sampling 24-Bit Delta Sigma ADC.
- fixed input range of +/- 11V.
- based on another new design with a DSP, RAM & ADC (ADS1274) combined and a differential serial link.
- The first design is 4-channel, but it may be expanded to 8 channels (ADS1278). - (8/2/10)
- Not clear if this will fit on a single FMC. Most likely a front-end with the ADC in a separate rack will be needed and the FMC will only contain some kind of digital receiver logic. (9/2/10)
- Users: TE/EPC 64 channels; SVC project (11x64 signals).
- 2.5 MSPS, 24-bit ADC, 1 channel, +/- 10V input, auto-calibration,
trigger by machine timing (CERN TE/MSC, Giloteaux)
- User: Train-B systems of AD, LEIR, PS, Booster and SPS. End 2010 prototype.
Digital to Analog Converters
- FMC3: 10MSPS, 4 channel, 16 bit, output range +/-10V. - Project will not start before 2011
High-performance Time-to-Digital Converter
- FMC6: To be designed (CERN BE/CO) by July 2010 for TE/ABT - User: Carlier
Fine Delay module
- FMC7: To be designed (CERN BE/CO) by June 2010 for TE/ABT - User: Carlier
FPGA Mezzanine Card (FMC) standard
- ANSI/VITA 57.1-2008 FPGA Mezzanine Card (FMC) Standard
-
VITAs description of FMC
**** VMEbus International Trade Association -
ANSI/VITA 57.1-2008 Specification (CERN users
only)
**** Attention: the final specification has serious changes on several clock lines If at CERN, contact Main.ErikVanDerBij, else contact VITA.
-
VITAs description of FMC
The FMC standard refers to other standards for the EEPROM data:
-
Intelligent Platform Management Interface
(Intel)
- PMI Platform Management FRU Information Storage Definition V1.0 Document Revision 1.1:http://download.intel.com/design/servers/ipmi/FRU1011.pdf
- Base IPMI commands defined in the PICMG 2.9 specification (CompactPCI System Management)
FMC components
Commercial FMC mezzanines
Commercial FMC carriers
- Curtis-Wright
Other links
- FMC Alliance (not much info)
- Adopting VITA 57 (FMC): Reducing FPGA I/O headaches
- A Brief History of FMC (VITA-57), fun background
-- ErikVanDerBij - 26 February 2010