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# Project description
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Actually this is not a hardware project, but is there to help you find
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your way in the VITA 57.1 FPGA Mezzanine Card (FMC) standard. It
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alsoshows you which FMC Mezzanines and Carriers are developed in the
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context of the Open Hardware project. Furthermore it gives practical
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info that can help you in designing FMC
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your way in the VITA 57.1 FPGA Mezzanine Card (FMC) standard. It also
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shows you which FMC Mezzanines and Carriers are developed in the context
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of the Open Hardware project. Furthermore it gives practical info that
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can help you in designing FMC
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modules.
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![](/uploads/ccfd6c8e952c36f01faeb8449eab03d8/fmc_singlewide.jpg)
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-----
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- [FMC cards developed as Open Hardware](OHR-developments)
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- [FMC product directories (non Open Hardware
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developments)](FMC-Product-dir)
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- [FMC standard info](FMC-standard)
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- [FMC components and design notes](FMC-usage-notes)
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- [FMC product directory (Open Hardware)](OHR-developments)
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- [FMC product directories (non Open Hardware)](FMC-Product-dir)
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- [FMC components and design tips](FMC-usage-notes)
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-----
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## OHR developments
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-----
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### FMC Carriers
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-----
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- [PCI Express Carrier with 1 FMC slot (LPC). Xilinx
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*Spartan*](https://www.ohwr.org/project/fmc-pci-carrier) (CERN
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BE/CO, P.Alvarez)
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- [Simple PCIe FMC carrier (SPEC). Xilinx
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*Spartan*](https://www.ohwr.org/project/spec/wiki) (CERN BE/CO +
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industry)
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- [VME FMC Carrier with 2 FMC slots (LPC). Xilinx
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*Spartan*](https://www.ohwr.org/project/fmc-vme-carrier) (CERN
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BE/BI, A.Boccardi)
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- [VME FMC Carrier with 2 FMC slots (HPC). Xilinx *Virtex* and Sharc
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DSP](https://www.ohwr.org/project/vxs-dsp-fmc-carrier) (CERN BE/RF,
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J. Molendijk)
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### FMC Mezzanines
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-----
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#### Digital I/O
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- [16-channel TTL I/O](https://www.ohwr.org/project/fmc-dio-16chttla)
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(CERN BE/CO, M.Cattin) - prototype produced. Needs redesign for
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other connector (15/2/10)
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- programmable as 8 in/8 out, 16 in or 16 out.
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#### Analog to Digital Converters
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Overview of specifications of CERN developments at
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[FMCAdcProjects](FMCAdcProjects).
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- [FmcAdc100M14b4cha: 100 MSPS, 14 bits, 4
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channel](https://www.ohwr.org/project/fmc-adc-100m14b4cha) (CERN
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BE/CO) - [prototypes
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tested](https://www.ohwr.org/project/fmc-adc-100m14b4cha/wiki#status)
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(October 2010)
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- Users
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- BPM Linac4. To be used on VME carrier (CERN BE/BI, L.Soby,
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M.Sordet, J.Belleman 1st beam end 2010)
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- [Booster Trajectory Measurement
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System](http://jeroen.web.cern.ch/jeroen/btms/btms.html)
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- OASIS general purpose (Deghaye)
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- PSB pick-ups, 64 cards needed on PCIe or VME (Belleman -
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BE/BI, end 2010)
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- [TERA Hadron therapy](http://www.tera.it/ise.cgi?lang=2),
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used on specific carrier with USB (N. Malakhov - PH/UGC,
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received prototype 25/10/2010)
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- [Agata experiment](http://agata.pd.infn.it/) (M. Bellato -
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INFN PH/UCM, August 2010, may require 400 cards)
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- [Culham Centre for Fusion Energy](http://www.ccfe.ac.uk/)
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(G. Naylor - CCFE, Aug 2010)
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- Advanced Photon Source, Argonne National Laboratory (A.
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Pietryla - APS-controls group - Jan 2011)
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<!-- end list -->
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- [FmcAdc100k16b8cha: 100 kSPS, 16 bits, 8
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channel](https://www.ohwr.org/project/fmc-adc-100k16b8cha) (CERN
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BE/CO) - being designed
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<!-- end list -->
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- 128 ksps ADC (CERN TE/EPC, Q. King, G. Ramseier) - under design
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- 128 kSPS (50 kHz bandwidth) with an ADS1274 Simultaneous
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Sampling 24-Bit Delta Sigma ADC.
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- fixed input range of +/- 11V.
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- based on another new design with a DSP, RAM & ADC (ADS1274)
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combined and a differential serial link.
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- The first design is 4-channel, but it may be expanded to 8
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channels (ADS1278). - (8/2/10)
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- Not clear if this will fit on a single FMC. Most likely a
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front-end with the ADC in a separate rack will be needed and the
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FMC will only contain some kind of digital receiver logic.
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(9/2/10)
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- Will use with PCIe carrier.
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- User: TE/EPC 64 channels; SVC project (Static Var Compensators,
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11x64 signals).
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<!-- end list -->
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- 125 MSPS, 16 bits, 4 channel ADC (CERN BE/RF,
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[J.Sanchez](http://consult.cern.ch/xwho/people/549249))
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- 50 Ohm DC-coupled, 70dBFS dynamic range, ENOB ~12, 40MHz analog
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bandwidth, +/-1V, gain selectable: 0dB/+24dB, thermal offset
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drift compensation.
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- Two low jitter clock inputs and two data clock outputs.
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- Design data: [EDMS
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EDA-02068](https://edms.cern.ch/nav/eda-02068).
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- Prototype received (October 2010).
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- *Needs carrier with HPC connector.*
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<!-- end list -->
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- 2.5 MSPS, 24-bit ADC, 1 channel, +/- 10V input, auto-calibration,
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trigger by machine timing (CERN TE/MSC, Giloteaux)
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- User: Train-B systems of AD, LEIR, PS, Booster and SPS. End 2010
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prototype.
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#### Digital to Analog Converters
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- [FMC3: 10MSPS, 4 channel, 16 bit, output range
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+/-10V.](https://www.ohwr.org/project/fmc-dac1) - (CERN BE/CO),
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Project will not start before 2011
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<!-- end list -->
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- FmcDac4ch16b125MSPS, 4 channel, 16 bit, 125 MSPS DAC (CERN BE/RF,
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P.M. Leinonen), schematics ready (April 2010)
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- 40 MHz analog BW, AC-coupled, 50 Ohm, 2Vpp or 2Vpp/16 output,
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4xSMC, clock generated on MDDS mezzanine output on SMC.
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- *Needs carrier with HPC connector.*
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#### High-performance Time-to-Digital Converter
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- FMC6: [FMC Time to Digital Converter: 5 channel, 1 ns
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resolution](https://www.ohwr.org/project/fmc-tdc)
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- Users
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- E. Carlier (TE/ABT), 1 ns resolution, may use [16-channel
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TTL I/O](https://www.ohwr.org/project/fmc-dio-16chttla) for
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I/O or NIM input?
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- A. Boccardi (BE/BI, Synchrotron light monitor), 50 ps
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resolution, likely another design requiring other front-end.
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#### Fine Delay module
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- [FMC-Delay-1ns-8cha: 4 channel, 1 ns
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resolution](https://www.ohwr.org/project/fmc-delay-1ns-8cha) (CERN
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BE/CO) - Schematics reviewed (November 2010)
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- ideas:
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http://gkasprow.selfip.com/~pkasprow/Creotech/products.pdf (page
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5)
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- Users
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- TE/ABT: Carlier
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- CTF3: E.Said (now uses VME board)
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#### Direct Digital Synthesizer
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- 0-125 MHz DDS (CERN BE/RF,
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[J.Sanchez](http://consult.cern.ch/xwho/people/549249))
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- Generates two independent clocks, one 10 MHz reference clock
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input
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- *Needs carrier with HPC connector.*
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#### Test cards
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- [FMC Connector tester - Mezzanine to test correct mounting of FMC
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connectors in FMC carrier
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boards.](https://www.ohwr.org/project/fmc-conn-tester)
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- GLIB - GBT Link Interface Board - AMC carrier
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- [OHR Project page](https://www.ohwr.org/project/glib)
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- [GLIB-project public
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page](https://espace.cern.ch/project-GBLIB/public/default.aspx)
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- [Design data](https://edms.cern.ch/nav/eda-02189)
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-----
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## FPGA Mezzanine Card (FMC) standard info
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-----
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### FMC standard
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- ANSI/VITA 57.1-2008 FPGA Mezzanine Card (FMC) Standard
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- [FMC Marketing Alliance](http://www.vita.com/fmc.html)
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- [VMEbus International Trade
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Association](http://www.vita.com)
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- [ANSI/VITA 57.1 Specification - CERN users only
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-](http://cdsweb.cern.ch/record/1172409?ln=en)
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The FMC standard refers to other standards for the EEPROM data:
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- [Intelligent Platform Management Interface
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(Intel)](http://www.intel.com/design/servers/ipmi/)
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- [PMI Platform Management FRU Information Storage Definition V1.0
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Document
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Revision 1.1](http://download.intel.com/design/servers/ipmi/FRU1011.pdf)
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- Base IPMI commands defined in the PICMG 2.9 specification
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(CompactPCI System Management)
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- [PICMG specifications
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website](http://www.picmg.org/v2internal/specifications.htm)
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- [CERN Library: System management specification: compact PCI
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PICMG 2.9 R1.0 ;
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ECN 2.9-1.0-001](http://cdsweb.cern.ch/cdslib/item_info?sysno=002801547)
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-----
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### FMC components
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- [Front-panels - XTech, Part no. XFM85-0001 (10mm
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height)](http://www.xtech-outside.com/products/atca_amc_fp.html)
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- [AdvancedMC FMC Bezels and Faceplates Product
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catalog](http://www.xtech-outside.com/products/catalogs/AMC_Bezels.pdf)
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- [Example order - CERN
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only](https://edh.cern.ch/Document/SupplyChain/DAI/4246041)
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- Spacers
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- CERN Stores: 06.61.91.313.1 (10 mm)
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- [Example order - CERN
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only](https://edh.cern.ch/Document/SupplyChain/MAG/4362352)
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- Schroff:
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[60897-278](http://new.schroff.de/catalogue/catalogue.do?OID=00000000000055cd0001003a&forward=showProductDetails&favOid=00000000000055cd0001003a&catId=DE&act=showBookmark&lang=en)
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- Screws 2.5mm x 6mm (diameter x length)
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- CERN Stores (Bossard): 1243896
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- [Example order - CERN
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only](https://edh.cern.ch/Document/SupplyChain/MAG/4362352)
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- [FMC connectors -
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Samtech](http://www.samtec.com/search/vita57fmc.aspx)
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- [Example order 1 - CERN
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only](https://edh.cern.ch/Document/SupplyChain/DAI/4233545)
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- [Example order 2 - CERN
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only](https://edh.cern.ch/Document/SupplyChain/DAI/4452669)
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### Connectors usable with 10mm FMC front-panel
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- SMC high-frequency front-panel mount connectors (low enough for 10mm
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FMC cards)
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- [Chin
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Nan 26-10-5-TGG](http://www.chinnan.com.tw/index.asp?unit=products&ID=1307&CatLevel=1&PID=3278)
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- [Johnson 131-6701-341](https://emersonconnectivity.com/OA_MEDIA/drawings/dr-1316701341.pdf)
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- [Survey of SMA, SMC and MMCX connectors for the use on FMC
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cards](https://www.ohwr.org/project/fmc-projects/uploads/64cc6a69f5b41319039e16add7001c1b/Connecteur_RF_pour_FMC.pdf)
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(in French)
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- [Example order - CERN
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only](https://edh.cern.ch/Document/SupplyChain/DAI/4331256)
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- Multi-pin connector
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- [Multi-pin Connectors for use on FMC front
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panels](FMC-Multi-pin)
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### PCIe front-panel with FMC cutout
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The PCI express boards designed as part of the OHR project need a
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specific front-panel with a cutout for the FMC carrier's front panel.
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- [Purcell Brackets](http://www.purcellbrackets.com/)
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- [Example order - CERN
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only](https://edh.cern.ch/Document/SupplyChain/DAI/4464028) -
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One-piece design
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- [Gompf Brackets](http://www.bracket.com/)
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- [Example order - CERN
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only](https://edh.cern.ch/Document/SupplyChain/DAI/4468499) -
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Three-piece design
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- Screws 3mm x 5mm (diameter x length)
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- CERN Stores (Bossard): 1244051
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- [Example order - CERN
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only](https://edh.cern.ch/Document/4557851)
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-----
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### FMC Usage notes
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- [Clocking guidelines for FMC
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Carriers](https://www.ohwr.org/project/fmc-projects/uploads/6737a6f140784d1e9d1ae47ccc003d3e/ClockingFMCs.pdf)
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-----
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### Product directories (non OHR developments)
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- [VITA Members FMC product
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directory](http://www.vita.com/proddir/productsearch.php?searchText=fmc&Submit=Find)
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### Non-commercial carriers (non OHR developments)
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- DESY
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- [DesyAMC 2 - AMC
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carrier](http://indico.cern.ch/getFile.py/access?contribId=167&sessionId=2&resId=1&materialId=slides&confId=83060)
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(page 17)
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### Commercial FMC mezzanines (non OHR developments)
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- [Creotech](http://creotech.pl/)
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- [Curtis Wright - A/D and D/A
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converters](http://www.cwcembedded.com/products/6/229/667.html)
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- [Dallas Logic - A/D
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converters](http://www.dallaslogic.com/products.htm)
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- [Integre Technologies - Camera link and custom
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designs](http://www.integretek.com/products2.html)
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- [Lyrtech](http://www.lyrtech.com/Products/Families/io_FMC.php)
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- FMC DSP board with 2 or 4 TI 6-core DSPs used for calculation
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boosting, equipped with PCIe Gen2 interface. Conceptual stage
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(15/11/2010)
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- FMC 2x 500MHz ADC, 12 bits for EAGLE experiment at Warsaw
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Laboratory of Heavy Ions - readout of germanium
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detectors.Conceptual stage (15/11/2010)
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- [16 channel
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ADC](http://picasaweb.google.com/kasprowg/FMC_16ChADC_photos#),
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10 bit, 130Mhz with 4 channel slow DAC. The FMC is up and
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running, code being written (15/11/2010)
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- [Xilinx FMC boards and
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kits](http://www.xilinx.com/products/boards_kits/fmc.htm)
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### Commercial FMC carriers (non OHR developments)
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- [Curtis-Wright](http://www.cwcembedded.com)
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- [6U VME, 2 FMC, FPE650 VPX Quad Virtex-5
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FPGA](http://www.cwcembedded.com/products/0/239/537.html)
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- [6U VME, 2 FMC, Dual-core 8640D 1GHz Dual Xilinx
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Virtex-5](http://www.cwcembedded.com/products/0/239/529.html)
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- [Other carriers](http://www.cwcembedded.com/P/6/279/632.html)
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- [Lyrtech](http://www.lyrtech.com)
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- [Perseus 601X AMC, 1 HPC FMC
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slot](http://www.lyrtech.com/Products/Perseus_601X.php)
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- [uDigitizer, FMC
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slots](http://www.lyrtech.com/Products/micro_Digitizer.php)
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- [Creotech](http://creotech.pl/)
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- FMC carrier for 18 or 36 FMC boards in a form of 2U/4U 19" rack.
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The schematics are almost finished (15/11/2010). We expect to
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have first prototypes in March. This will be used for 512
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channel GEM spectrometer. [Design
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prototype](http://picasaweb.google.com/kasprowg/DropBox?authkey=Gv1sRgCMPe08_hr_P7Cw#5509289780566938450)
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- Single FMC carrier with Virtex 4 with PowerPC and Gbit Ethernet
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interface to hold 2x500MHz card. Conceptual stage (15/11/2010)
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### Other links
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- [FMC Alliance](http://www.vita.com/fmc.html) - *refers to these OHR
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pages*
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- [Adopting VITA 57 (FMC): Reducing FPGA I/O
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headaches](http://www.mil-embedded.com/articles/id/?4141)
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- [A Brief History of FMC (VITA-57), fun
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background](http://atomicrules.blogspot.com/2009/12/brief-history-of-fmc-vita-57.html)
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-----
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Erik van der Bij - 18 January 2011
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Erik van der Bij - 20 January 2011
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