... | @@ -43,16 +43,23 @@ Overview of specifications of CERN developments at |
... | @@ -43,16 +43,23 @@ Overview of specifications of CERN developments at |
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- [FmcAdc100M14b4cha: 100 MSPS, 14 bits, 4
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- [FmcAdc100M14b4cha: 100 MSPS, 14 bits, 4
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channel](https://www.ohwr.org/project/fmc-adc-100m14b4cha) (CERN
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channel](https://www.ohwr.org/project/fmc-adc-100m14b4cha) (CERN
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BE/CO) - being designed
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BE/CO) - prototype being built
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- User: BPM Linac4. To be used on VME carrier (L.Soby, M.Sordet
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- User: BPM Linac4. To be used on VME carrier (L.Soby, M.Sordet
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1st beam end 2010)
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1st beam end 2010)
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- User: OASIS general purpose (Deghaye)
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- User: OASIS general purpose (Deghaye)
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- User: PSB pick-ups, 64 cards needed on PCIe or VME (Belleman -
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- User: PSB pick-ups, 64 cards needed on PCIe or VME (Belleman -
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BE/BI, end 2010)
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BE/BI, end 2010)
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- [FmcAdc100k16b8cha: 100 kSPS, 16 bits, 8
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channel](https://www.ohwr.org/project/fmc-adc-100k16b8cha) (CERN
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BE/CO) - being designed
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- FmcAdc1/FMC2: 100 MSPS, 2 channel, 14 bit max. with auto calibration
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- FmcAdc1/FMC2: 100 MSPS, 2 channel, 14 bit max. with auto calibration
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- (CERN BE/CO) - cancelled
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- (CERN BE/CO) - cancelled, replaced by
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- FmcAdc2/FMC1: 1 MSPS, 8 channel, 16 bit max. (CERN BE/CO) - design
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[FmcAdc100M14b4cha](https://www.ohwr.org/project/fmc-adc-100m14b4cha)
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not started
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- FmcAdc2/FMC1: 1 MSPS, 8 channel, 16 bit max. (CERN BE/CO) - replaced
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by
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[FmcAdc100k16b8cha](https://www.ohwr.org/project/fmc-adc-100k16b8cha)
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- 128 ksps ADC (CERN TE/EPC, Q. King, G. Ramseier) - under design
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- 128 ksps ADC (CERN TE/EPC, Q. King, G. Ramseier) - under design
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- 128 kSPS (50 kHz bandwidth) with an ADS1274 Simultaneous
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- 128 kSPS (50 kHz bandwidth) with an ADS1274 Simultaneous
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Sampling 24-Bit Delta Sigma ADC.
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Sampling 24-Bit Delta Sigma ADC.
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... | @@ -68,9 +75,6 @@ Overview of specifications of CERN developments at |
... | @@ -68,9 +75,6 @@ Overview of specifications of CERN developments at |
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- Will use with PCIe carrier.
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- Will use with PCIe carrier.
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- Users: TE/EPC 64 channels; SVC project (Static Var Compensators,
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- Users: TE/EPC 64 channels; SVC project (Static Var Compensators,
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11x64 signals).
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11x64 signals).
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<!-- end list -->
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- 2.5 MSPS, 24-bit ADC, 1 channel, +/- 10V input, auto-calibration,
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- 2.5 MSPS, 24-bit ADC, 1 channel, +/- 10V input, auto-calibration,
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trigger by machine timing (CERN TE/MSC, Giloteaux)
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trigger by machine timing (CERN TE/MSC, Giloteaux)
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- User: Train-B systems of AD, LEIR, PS, Booster and SPS. End 2010
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- User: Train-B systems of AD, LEIR, PS, Booster and SPS. End 2010
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... | @@ -181,7 +185,7 @@ The FMC standard refers to other standards for the EEPROM data: |
... | @@ -181,7 +185,7 @@ The FMC standard refers to other standards for the EEPROM data: |
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- [A Brief History of FMC (VITA-57), fun
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- [A Brief History of FMC (VITA-57), fun
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background](http://atomicrules.blogspot.com/2009/12/brief-history-of-fmc-vita-57.html)
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background](http://atomicrules.blogspot.com/2009/12/brief-history-of-fmc-vita-57.html)
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\-- ErikVanDerBij - 30 March 2010
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\-- ErikVanDerBij - 14 April 2010
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