... | @@ -19,6 +19,168 @@ modules. |
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## OHR developments
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### FMC Carriers
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- [PCI Express Carrier with 1 FMC slot (LPC). Xilinx
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*Spartan*](https://www.ohwr.org/project/fmc-pci-carrier) (CERN
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BE/CO, P.Alvarez)
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- [Simple PCIe FMC carrier (SPEC). Xilinx
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*Spartan*](https://www.ohwr.org/project/spec/wiki) (CERN BE/CO +
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industry)
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- [VME FMC Carrier with 2 FMC slots (LPC). Xilinx
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*Spartan*](https://www.ohwr.org/project/fmc-vme-carrier) (CERN
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BE/BI, A.Boccardi)
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- [VME FMC Carrier with 2 FMC slots (HPC). Xilinx *Virtex* and Sharc
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DSP](https://www.ohwr.org/project/vxs-dsp-fmc-carrier) (CERN BE/RF,
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J. Molendijk)
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### FMC Mezzanines
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#### Digital I/O
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- [16-channel TTL I/O](https://www.ohwr.org/project/fmc-dio-16chttla)
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(CERN BE/CO, M.Cattin) - prototype produced. Needs redesign for
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other connector (15/2/10)
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- programmable as 8 in/8 out, 16 in or 16 out.
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#### Analog to Digital Converters
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Overview of specifications of CERN developments at
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[FMCAdcProjects](FMCAdcProjects).
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- [FmcAdc100M14b4cha: 100 MSPS, 14 bits, 4
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channel](https://www.ohwr.org/project/fmc-adc-100m14b4cha) (CERN
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BE/CO) - [prototypes
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tested](https://www.ohwr.org/project/fmc-adc-100m14b4cha/wiki#status)
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(October 2010)
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- Users
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- BPM Linac4. To be used on VME carrier (CERN BE/BI, L.Soby,
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M.Sordet, J.Belleman 1st beam end 2010)
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- [Booster Trajectory Measurement
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System](http://jeroen.web.cern.ch/jeroen/btms/btms.html)
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- OASIS general purpose (Deghaye)
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- PSB pick-ups, 64 cards needed on PCIe or VME (Belleman -
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BE/BI, end 2010)
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- [TERA Hadron therapy](http://www.tera.it/ise.cgi?lang=2),
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used on specific carrier with USB (N. Malakhov - PH/UGC,
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received prototype 25/10/2010)
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- [Agata experiment](http://agata.pd.infn.it/) (M. Bellato -
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INFN PH/UCM, August 2010, may require 400 cards)
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- [Culham Centre for Fusion Energy](http://www.ccfe.ac.uk/)
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(G. Naylor - CCFE, Aug 2010)
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- Advanced Photon Source, Argonne National Laboratory (A.
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Pietryla - APS-controls group - Jan 2011)
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<!-- end list -->
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- [FmcAdc100k16b8cha: 100 kSPS, 16 bits, 8
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channel](https://www.ohwr.org/project/fmc-adc-100k16b8cha) (CERN
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BE/CO) - being designed
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<!-- end list -->
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- 128 ksps ADC (CERN TE/EPC, Q. King, G. Ramseier) - under design
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- 128 kSPS (50 kHz bandwidth) with an ADS1274 Simultaneous
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Sampling 24-Bit Delta Sigma ADC.
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- fixed input range of +/- 11V.
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- based on another new design with a DSP, RAM & ADC (ADS1274)
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combined and a differential serial link.
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- The first design is 4-channel, but it may be expanded to 8
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channels (ADS1278). - (8/2/10)
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- Not clear if this will fit on a single FMC. Most likely a
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front-end with the ADC in a separate rack will be needed and the
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FMC will only contain some kind of digital receiver logic.
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(9/2/10)
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- Will use with PCIe carrier.
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- User: TE/EPC 64 channels; SVC project (Static Var Compensators,
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11x64 signals).
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<!-- end list -->
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- 125 MSPS, 16 bits, 4 channel ADC (CERN BE/RF,
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[J.Sanchez](http://consult.cern.ch/xwho/people/549249))
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- 50 Ohm DC-coupled, 70dBFS dynamic range, ENOB ~12, 40MHz analog
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bandwidth, +/-1V, gain selectable: 0dB/+24dB, thermal offset
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drift compensation.
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- Two low jitter clock inputs and two data clock outputs.
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- Design data: [EDMS
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EDA-02068](https://edms.cern.ch/nav/eda-02068).
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- Prototype received (October 2010).
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- *Needs carrier with HPC connector.*
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<!-- end list -->
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- 2.5 MSPS, 24-bit ADC, 1 channel, +/- 10V input, auto-calibration,
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trigger by machine timing (CERN TE/MSC, Giloteaux)
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- User: Train-B systems of AD, LEIR, PS, Booster and SPS. End 2010
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prototype.
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#### Digital to Analog Converters
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- [FMC3: 10MSPS, 4 channel, 16 bit, output range
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+/-10V.](https://www.ohwr.org/project/fmc-dac1) - (CERN BE/CO),
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Project will not start before 2011
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<!-- end list -->
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- FmcDac4ch16b125MSPS, 4 channel, 16 bit, 125 MSPS DAC (CERN BE/RF,
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P.M. Leinonen), schematics ready (April 2010)
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- 40 MHz analog BW, AC-coupled, 50 Ohm, 2Vpp or 2Vpp/16 output,
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4xSMC, clock generated on MDDS mezzanine output on SMC.
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- *Needs carrier with HPC connector.*
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#### High-performance Time-to-Digital Converter
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- FMC6: [FMC Time to Digital Converter: 5 channel, 1 ns
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resolution](https://www.ohwr.org/project/fmc-tdc)
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- Users
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- E. Carlier (TE/ABT), 1 ns resolution, may use [16-channel
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TTL I/O](https://www.ohwr.org/project/fmc-dio-16chttla) for
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I/O or NIM input?
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- A. Boccardi (BE/BI, Synchrotron light monitor), 50 ps
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resolution, likely another design requiring other front-end.
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#### Fine Delay module
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- [FMC-Delay-1ns-8cha: 4 channel, 1 ns
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resolution](https://www.ohwr.org/project/fmc-delay-1ns-8cha) (CERN
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BE/CO) - Schematics reviewed (November 2010)
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- ideas:
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http://gkasprow.selfip.com/~pkasprow/Creotech/products.pdf (page
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5)
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- Users
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- TE/ABT: Carlier
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- CTF3: E.Said (now uses VME board)
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#### Direct Digital Synthesizer
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- 0-125 MHz DDS (CERN BE/RF,
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[J.Sanchez](http://consult.cern.ch/xwho/people/549249))
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- Generates two independent clocks, one 10 MHz reference clock
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input
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- *Needs carrier with HPC connector.*
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#### Test cards
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- [FMC Connector tester - Mezzanine to test correct mounting of FMC
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connectors in FMC carrier
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boards.](https://www.ohwr.org/project/fmc-conn-tester)
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- GLIB - GBT Link Interface Board - AMC carrier
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- [OHR Project page](https://www.ohwr.org/project/glib)
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- [GLIB-project public
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page](https://espace.cern.ch/project-GBLIB/public/default.aspx)
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- [Design data](https://edms.cern.ch/nav/eda-02189)
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## FPGA Mezzanine Card (FMC) standard info
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## FPGA Mezzanine Card (FMC) standard info
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