PLL_OUT on CLK0_M2C_P
Check if it is acceptable to connect PLL_OUT to CLK0_M2C_P.
VITA 57.1 standard, rule 5.20, says
CLK0_C2M, CLK0_M2C, CLK1_C2M, CLK1_M2C shall use the LVDS signaling standard.
Another option could be to use a clock capable user pin like LA00_P_CC (G6), although it's only a recommendation in the standard that the carrier connects it to a clock capable FPGA pin.