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BI might be interested in having an I2C master for the reconfiguration of the LpGBTx.
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For the implementation the following options might be feasible; a proof-of-concept is needed for confirmation.
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### A. JTAG-like implementation
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- Similar to the JTAG feature: bitbanging of 124-bytes after the reception of a full WorldFIP frame
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- Reception of a complete variable, regardless of the node configuration i.e. stand-alone or not
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- Data storage in the memory
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- Dedicated pins and clock generation internally in nanoFIP
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- Impact on hw/ gw/ sw:
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- gw & sw: addition of new variable or possibly tweaking of the JTAG variable
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- sw: library for the generation of the frames-containing-I2C
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- gw: driving/receiving the I2C signals
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- hw: no impact; use of spare FMC lines
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### B. Using the DAT_O/I pins
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- Use of nanoFIP DAT_O/I pins in standalone mode:
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- DAT_O pins: SCL_O, SDA_O, SDA_OE_O
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- DAT_I pins: SDA_I
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- Carrier board to combine the unidirectional nanoFIP I/Os to the bidirectional I2C SDA
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- SCL: we assume that having it unidirectional, coming from the FMC-nanoFIP and not supporting clock stretching, would be sufficient
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- Use of one WorldFIP frame for every I2C bit
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- Max estimated speed: 0,5 KHz on the I2C SCL (one clock transition per macrocycle; macrocyle dedicated to one node)
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- Impact on hw/ gw/ sw:
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- No gw changes in nanoFIP
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- Sw library for the generation of the frames-containing-I2C
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- Hw on the carrier to combine uni-directional signals to bidirectional
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- new software library for the generation of the frames
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### Open questions:
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- Access to the I2C interface out of the normal operation of the bus (with dedicated mactrocycle)
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- Frequency and timeouts on the LpGBTx I2C interface |
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\ No newline at end of file |