AIDA FMC TLU
Overview
A Trigger/Timing Logic Unit designed for use with High Energy Physics beam-tests. Provides a simple and flexible interface for fast timing and triggering signals at the AIDA pixel sensor beam-telescope. Implemented as a double-width FMC with single LPC connector. Compatible with EUDET JRA1 TLU.
( A prototype, the mini-TLU is described here: AIDA-Mini-TLU )
Specification
Parameter | Value |
Number of trigger inputs (scintillator, NIM , TTL) | 6 |
Trigger discriminator type | One Threshold, one CFD per input |
Trigger input voltage range | ± 5V max. |
Trigger input connector type | Lemo single-pole size-00 |
Trigger input termination | 50 Ohm. |
Trigger threshold range | ± 1.3V software controlled |
Trigger threshold accuracy | ± 5mV |
Number of clock I/O | 1 |
Clock I/O connector type | Lemo two-pole size-00 |
Clock I/O voltage levels | LVDS |
Clock I/O termination | 100 Ohm differential, if used as an input |
Number of connectors for "Devices Under Test" (DUT) | 4 |
DUT connector type | HDMI |
Number of signals per DUT | 5 |
DUT voltage levels | LVDS |
DUT signal termination | 100 Ohm differential for inputs |
Hardware
The database files for the schematic capture ( Cadence HDL ) and PCB layout ( Cadence Allegro ) are available in the project Subversion respository: http://svn.ohwr.org/fmc-mtlu/trunk/circuit_board
A circuit schematic in PDF format is available here: http://svn.ohwr.org/fmc-mtlu/trunk/circuit_board/Schematics/fmc_tlu_v1a.pdf
Firmware
The TLU communicates over a Gigabit serial link using the IPBus protocol: https://svnweb.cern.ch/trac/cactus/wiki , https://ipbus.web.cern.ch/ipbus/
A description of the firmware (produced by Doxygen from comments in the code) is found here: http://svn.ohwr.org/fmc-mtlu/trunk/documents/firmware/doxygen/output/html/index.html
Instructions on building the firmware are found here: FirmwareBuild-FMC-TLU
Details of how to simulate the firmware are found here: SimulationEnvironment-FMC-TLU
Software
For testing purposes the TLU can be controlled/read-out using Python
scripts using the PyChips or uHAL libraries. These scripts can be found
here:
http://svn.ohwr.org/fmc-mtlu/trunk/firmware/scripts . One of the scripts
startTLU.py allows time-stamp data to be read out and stored in a Root
file. startTLU-instructions
The TLU is fully integrated into the EUDAQ framework ( see: http://eudaq.hepforge.org/ ).
Network
The TLU communicates with a host-PC over Gigabit/s Ethernet using the IPBus protocol layered on top of UDP/IP.
With the current firmware version the IP address of the TLU FPGA is set
to 192.168.200.30 . In a future release it will be possible to change
this by programming an on-board PROM
---
Testing hardware
Details of how to test the miniTLU hardware, and test results from existing miniTLUs can be found here: Hardware-Testing
Project Documents
A short "User Manual" for the mini-TLU is available here: http://svn.ohwr.org/fmc-mtlu/trunk/documents/firmware/latex/AIDA_TLU_note.pdf
Interface to CALICE Timing System ( CCC )
The AIDA-2020 TLU can interface to the Clock and Control Card of the CALICE Calorimetry development project. Details can be found here: TLU-to-CCC-Interface
Reporting Problems
Use the bug-tracker to report bug/problems/suggestions : https://www.ohwr.org/work_packages/new
Monitor existing issues here: https://www.ohwr.org/project/fmc-mtlu/issues
Status
| Date| * Event *|
|
| 10-Feb-2011 | Creation of AIDA Mini-TLU project in OHWR. |
| 18-Feb-2011 | AIDA Kick-off meeting at CERN. Initial specification of
mTLU |
| March-2013 | First prototype version of TLU available for tests|
| January-2014 | Second prototype version of TLU available for tests|
| May-2016 | Schematic capture started on third prototype |
| June-2016 | Schematic for third prototype ready for review|
Useful References
- Description of the JRA1 Trigger Logic Unit (TLU), v0.2c , EUDET-Memo-2009-4
- Talks/posters ( at meeting, conferences )
David Cussans - 8 May 2018