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AIDA-2020 TLU
Commits
cd30c695
Commit
cd30c695
authored
Dec 04, 2014
by
David Cussans
Browse files
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Plain Diff
Added code to sync. trig line onto 40MHz clock
parent
a69bb46c
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13 changed files
with
1814 additions
and
2190 deletions
+1814
-2190
DUTInterfaces_rtl.vhd
firmware/hdl/common/DUTInterfaces_rtl.vhd
+96
-27
IPBusInterface_rtl.vhd
firmware/hdl/common/IPBusInterface_rtl.vhd
+1
-1
ipbus_addr_decode.vhd
firmware/hdl/common/ipbus_addr_decode.vhd
+2
-10
ipbus_ver.vhd
firmware/hdl/common/ipbus_ver.vhd
+1
-1
top_extphy_struct.vhd
firmware/hdl/miniTLU/top_extphy_struct.vhd
+7
-8
.cache.dat
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.cache.dat
+0
-0
top_extphy_struct.xrf
...gner/fmc_mTLU/fmc_mTLU_lib/hds/.xrf/top_extphy_struct.xrf
+335
-338
struct.bd
...l_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd
+961
-1198
struct.bd.bak
...signer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd.bak
+384
-584
symbol.sb
...l_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/symbol.sb
+16
-15
aida_mini_tlu_addr_map.txt
firmware/scripts/aida_mini_tlu_addr_map.txt
+3
-1
test_aida_tlu_thresholds.py
firmware/scripts/test_aida_tlu_thresholds.py
+1
-1
test_aida_tlu_trig_counter.py
firmware/scripts/test_aida_tlu_trig_counter.py
+7
-6
No files found.
firmware/hdl/common/DUTInterfaces_rtl.vhd
View file @
cd30c695
...
...
@@ -21,10 +21,14 @@
--! @details
--! Address map:\n
--! 5-bit decoded
--! 0x00000000 - DUT mask ( write )
--! 0x0000000
--! 0x00000000 - DUT interface mode, two bits per DUT. Up to 12 inputs XXXXXXXXBBAA99887766554433221100\n
--! - mode: 0 = EUDET mode , 1 = synchronous ( LHC / Timepix ) , 2,3=reserved
--! mode: 0 = EUDET mode , 1 = synchronous ( LHC / Timepix ) , 2,3=reserved\n
--! 0x00000001 - DUT mask. 1 = active , 0 = inactive. Inactive DUT don't contribute to BUSY. \n
--! Up to 12 inputs. One bit per DUT XXXXXXXXXXXXXXXXXXXXXXBA9876543210\n
--!
--!
--
--!
--! <b>Dependencies:</b>\n
--!
...
...
@@ -92,14 +96,22 @@ ARCHITECTURE rtl OF DUTInterfaces IS
signal
s_veto
:
std_logic
;
signal
s_strobe_4x_logic_d1
:
std_logic
;
signal
s_clk_to_DUT
,
s_busy_from_dut
,
s_reset_or_clk_to_dut
,
s_trigger_to_dut
:
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
);
signal
s_DUT_mask
:
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
)
:
=
(
others
=>
'0'
);
--! Mask for the DUTs
not used
signal
s_
clk_is_input
,
s_clk_is_input_b
:
std_logic
:
=
'0'
;
--! Indicates the direction of the clock in the RJ45 DUT
signal
s_DUT_mask
:
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
)
:
=
(
others
=>
'0'
);
--! Mask for the DUTs
used. 1 = active
signal
s_
DUT_ignore_busy
:
std_logic_vector
(
g_NUM_DUTS
-1
downto
0
)
:
=
(
others
=>
'0'
);
--! set bit to 1 for BUSY to be ignored.
signal
s_clk_to_tlu
:
std_logic
:
=
'0'
;
constant
c_N_CTRL
:
positive
:
=
1
;
constant
c_N_STAT
:
positive
:
=
1
;
constant
c_N_CTRL
:
positive
:
=
2
;
constant
c_N_STAT
:
positive
:
=
2
;
signal
s_status_to_ipbus
,
s_sync_status_to_ipbus
:
ipb_reg_v
(
c_N_STAT
-1
downto
0
);
signal
s_control_from_ipbus
,
s_sync_control_from_ipbus
:
ipb_reg_v
(
c_N_CTRL
-1
downto
0
);
signal
s_dut_clk
:
std_logic
:
=
'0'
;
-- ! internal clock that gets copied to DUT outputs
signal
s_dut_clk_sr
:
std_logic_vector
(
2
downto
0
)
:
=
"001"
;
--! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
signal
s_stretch_trig_in
:
std_logic
:
=
'0'
;
-- ! stretched version of trigger_i
signal
s_stretch_trig_in_sr
:
std_logic_vector
(
2
downto
0
)
:
=
"111"
;
--! Gets shifted out by clk_4x logic. Loaded by trigger_i
signal
s_trigger_out
:
std_logic
:
=
'0'
;
-- ! trigger shifted to start on strobe_4x_logic
signal
s_trigger_out_sr
:
std_logic_vector
(
2
downto
0
)
:
=
"111"
;
--! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
signal
s_trigger_out_vector
:
std_logic_vector
(
s_trigger_to_dut
'range
)
:
=
(
others
=>
'0'
);
-- Nasty bodge - vector copy of s_trigger_out
BEGIN
...
...
@@ -147,9 +159,11 @@ BEGIN
-- Map the control registers
s_DUT_mask
<=
s_sync_control_from_ipbus
(
0
)(
g_NUM_DUTS
-1
downto
0
);
s_DUT_ignore_busy
<=
s_sync_control_from_ipbus
(
1
)(
g_NUM_DUTS
-1
downto
0
);
-- Map the status registers
s_status_to_ipbus
(
0
)
<=
std_logic_vector
(
to_unsigned
(
0
,
g_IPBUS_WIDTH
-
g_NUM_DUTS
))
&
s_DUT_mask
;
s_status_to_ipbus
(
1
)
<=
std_logic_vector
(
to_unsigned
(
0
,
g_IPBUS_WIDTH
-
g_NUM_DUTS
))
&
s_DUT_ignore_busy
;
duts
:
for
dut
in
1
to
g_NUM_DUTS
generate
...
...
@@ -181,7 +195,7 @@ BEGIN
port
map
(
O
=>
trigger_to_dut_p_o
(
dut
-1
),
-- Diff_p output (connect directly to top-level port)
OB
=>
trigger_to_dut_n_o
(
dut
-1
),
-- Diff_n output (connect directly to top-level port)
I
=>
s_trigger_to_dut
(
dut
-1
)
and
s_DUT_mask
(
dut
-1
)
-- Buffer input
I
=>
s_trigger_to_dut
(
dut
-1
)
-- Buffer input
);
clk_rst_OBUFDS_inst
:
OBUFDS
...
...
@@ -194,28 +208,81 @@ BEGIN
);
s_intermediate_busy_or
(
dut
)
<=
s_intermediate_busy_or
(
dut
-1
)
or
(
s_busy_from_dut
(
dut
-1
)
and
s_DUT_mask
(
dut
-1
));
(
s_busy_from_dut
(
dut
-1
)
and
s_DUT_mask
(
dut
-1
)
and
(
not
s_DUT_ignore_busy
(
dut
-1
))
);
ddr_for_clk_output
:
ODDR2
generic
map
(
DDR_ALIGNMENT
=>
"NONE"
,
-- Sets output alignment to "NONE", "C0", "C1"
INIT
=>
'0'
,
-- Sets initial state of the Q output to '0' or '1'
SRTYPE
=>
"SYNC"
)
-- Specifies "SYNC" or "ASYNC" set/reset
port
map
(
Q
=>
s_clk_to_dut
(
dut
-1
),
-- 1-bit output data
C0
=>
clk_to_dut_i
,
-- 1-bit clock input
C1
=>
not
clk_to_dut_i
,
-- 1-bit clock input
CE
=>
'1'
,
-- 1-bit clock enable input
D0
=>
'1'
,
-- 1-bit data input (associated with C0)
D1
=>
'0'
,
-- 1-bit data input (associated with C1)
R
=>
'0'
,
-- 1-bit reset input
S
=>
'0'
-- 1-bit set input
);
--
ddr_for_clk_output : ODDR2
--
generic map(
--
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
--
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
--
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
--
port map (
--
Q => s_clk_to_dut(dut-1), -- 1-bit output data
--
C0 => clk_to_dut_i, -- 1-bit clock input
--
C1 => not clk_to_dut_i, -- 1-bit clock input
--
CE => '1', -- 1-bit clock enable input
--
D0 => '1', -- 1-bit data input (associated with C0)
--
D1 => '0', -- 1-bit data input (associated with C1)
--
R => '0', -- 1-bit reset input
--
S => '0' -- 1-bit set input
--
);
end
generate
duts
;
-- purpose: generates a clock from 4x clock and strobe ( high once every 4 cycles )
-- should produce 11001100... etc. ie. 40MHz clock from 160MHz clock
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_i
-- outputs: s_dut_clk
p_dut_clk_gen
:
process
(
clk_4x_logic_i
,
strobe_4x_logic_i
)
is
begin
-- process p_dut_clk_gen
if
rising_edge
(
clk_4x_logic_i
)
then
if
(
strobe_4x_logic_i
=
'1'
)
then
s_dut_clk
<=
'1'
;
s_dut_clk_sr
<=
"001"
;
else
s_dut_clk
<=
s_dut_clk_sr
(
0
);
s_dut_clk_sr
<=
'0'
&
s_dut_clk_sr
(
s_dut_clk_sr
'left
downto
1
);
end
if
;
end
if
;
end
process
p_dut_clk_gen
;
-- purpose: re-times a single cycle pulse on trigger on clk_4x_logic onto clk_logic
-- type : combinational
-- inputs : clk_4x_logic_i , strobe_4x_logic_i , trigger_i
-- outputs: s_premask_trigger_to_dut
p_dut_trig_retime
:
process
(
clk_4x_logic_i
,
strobe_4x_logic_i
,
trigger_i
)
is
begin
-- process p_dut_trig_retime
if
rising_edge
(
clk_4x_logic_i
)
then
-- Stretch trigger_i pulse to 4 clock cycles on clk4x
if
trigger_i
=
'1'
then
s_stretch_trig_in
<=
'1'
;
s_stretch_trig_in_sr
<=
"111"
;
else
s_stretch_trig_in
<=
s_stretch_trig_in_sr
(
0
);
s_stretch_trig_in_sr
<=
'0'
&
s_stretch_trig_in_sr
(
s_stretch_trig_in_sr
'left
downto
1
);
end
if
;
--
if
(
strobe_4x_logic_i
=
'1'
)
and
(
s_stretch_trig_in
=
'1'
)
then
s_trigger_out
<=
'1'
;
s_trigger_out_sr
<=
"111"
;
else
s_trigger_out
<=
s_trigger_out_sr
(
0
);
s_trigger_out_sr
<=
'0'
&
s_trigger_out_sr
(
s_trigger_out_sr
'left
downto
1
);
end
if
;
s_trigger_to_dut
<=
s_DUT_mask
and
s_trigger_out_vector
;
end
if
;
end
process
p_dut_trig_retime
;
s_trigger_out_vector
<=
(
others
=>
s_trigger_out
);
s_veto
<=
s_intermediate_busy_or
(
g_NUM_DUTS
);
-- purpose: register for internal signals and output signals
...
...
@@ -228,8 +295,10 @@ BEGIN
veto_o
<=
s_veto
;
s_strobe_4x_logic_d1
<=
strobe_4x_logic_i
;
--s_reset_or_clk_to_dut <= ( others => (s_strobe_4x_logic_d1 or strobe_4x_logic_i));
s_trigger_to_dut
<=
(
others
=>
trigger_i
);
--
s_trigger_to_dut <= ( others => trigger_i );
--shutter_to_dut <= ( others => shutter_i );
--! Copy clock to array of clocks.
s_clk_to_dut
<=
(
others
=>
s_dut_clk
);
end
if
;
end
process
register_signals
;
...
...
firmware/hdl/common/IPBusInterface_rtl.vhd
View file @
cd30c695
...
...
@@ -42,7 +42,7 @@ USE ieee.std_logic_1164.all;
USE
ieee
.
numeric_std
.
all
;
USE
work
.
ipbus
.
all
;
use
work
.
emac_hostbus_decl
.
all
;
--
use work.emac_hostbus_decl.all;
ENTITY
IPBusInterface
IS
GENERIC
(
...
...
firmware/hdl/common/ipbus_addr_decode.vhd
View file @
cd30c695
...
...
@@ -35,18 +35,10 @@ package body ipbus_addr_decode is
sel
:
=
4
;
-- logic_clocks / base 000000a0 / mask 0000001f
elsif
std_match
(
addr
,
"-----------------------0110-----"
)
then
sel
:
=
5
;
-- i2c_master / base 000000c0 / mask 00000007
elsif
std_match
(
addr
,
"-----------------------0111-----"
)
then
sel
:
=
6
;
-- Trigger_Generator / base 000000e0 / mask 0000001f
elsif
std_match
(
addr
,
"-----------------------1000-----"
)
then
sel
:
=
7
;
-- Shutter_Generator / base 00000100 / mask 0000001f
elsif
std_match
(
addr
,
"-----------------------1001-----"
)
then
sel
:
=
8
;
-- Spill_Generator / base 00000120 / mask 0000001f
elsif
std_match
(
addr
,
"-----------------------1010-----"
)
then
sel
:
=
9
;
-- Event_Formatter / base 00000140 / mask 0000001f
elsif
std_match
(
addr
,
"-----------------------1011-----"
)
then
sel
:
=
10
;
-- Handshakes / base 00000160 / mask 0000001f
sel
:
=
6
;
-- Event_Formatter / base 00000140 / mask 0000001f
elsif
std_match
(
addr
,
"-----------------------0000-----"
)
then
sel
:
=
11
;
-- version / base 00000000 / mask 00000000
sel
:
=
7
;
-- version / base 00000000 / mask 00000000
else
sel
:
=
99
;
end
if
;
...
...
firmware/hdl/common/ipbus_ver.vhd
View file @
cd30c695
...
...
@@ -20,7 +20,7 @@ architecture rtl of ipbus_ver is
begin
ipbus_out
.
ipb_rdata
<=
X"a5
ee
"
&
X"1008"
;
-- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out
.
ipb_rdata
<=
X"a5
f0
"
&
X"1008"
;
-- Lower 16b are ipbus firmware build ID (temporary arrangement).
ipbus_out
.
ipb_ack
<=
ipbus_in
.
ipb_strobe
;
ipbus_out
.
ipb_err
<=
'0'
;
...
...
firmware/hdl/miniTLU/top_extphy_struct.vhd
View file @
cd30c695
...
...
@@ -2,7 +2,7 @@
--
-- Created:
-- by - phdgc.users (voltar.phy.bris.ac.uk)
-- at - 1
6:52:05 11/28
/14
-- at - 1
7:25:09 12/03
/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2012.2b (Build 5)
--
...
...
@@ -14,7 +14,7 @@ ENTITY top_extphy IS
GENERIC
(
g_NUM_DUTS
:
positive
:
=
3
;
g_NUM_TRIG_INPUTS
:
positive
:
=
4
;
g_NUM_EXT_SLAVES
:
positive
:
=
10
;
--! Number of slaves outside IPBus interface
g_NUM_EXT_SLAVES
:
positive
:
=
7
;
--! Number of slaves outside IPBus interface
g_EVENT_DATA_WIDTH
:
positive
:
=
64
;
g_IPBUS_WIDTH
:
positive
:
=
32
;
g_NUM_EDGE_INPUTS
:
positive
:
=
4
;
...
...
@@ -62,7 +62,7 @@ END top_extphy ;
--
-- Created:
-- by - phdgc.users (voltar.phy.bris.ac.uk)
-- at - 1
4:00:06 12/02
/14
-- at - 1
8:11:22 12/03
/14
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2012.2b (Build 5)
--
...
...
@@ -72,7 +72,7 @@ USE ieee.numeric_std.all;
LIBRARY
work
;
USE
work
.
ipbus
.
all
;
USE
work
.
emac_hostbus_decl
.
all
;
--
USE work.emac_hostbus_decl.all;
USE
work
.
fmcTLU
.
all
;
LIBRARY
unisim
;
...
...
@@ -93,7 +93,6 @@ ARCHITECTURE struct OF top_extphy IS
SIGNAL
event_number
:
std_logic_vector
(
g_IPBUS_WIDTH
-1
DOWNTO
0
);
-- starts at one. Increments for each post_veto_trigger
SIGNAL
ipbr
:
ipb_rbus_array
(
g_NUM_EXT_SLAVES
-1
DOWNTO
0
);
--! IPBus read signals
SIGNAL
ipbus_clk
:
std_logic
;
SIGNAL
ipbus_clk_i
:
std_logic
;
SIGNAL
ipbus_reset
:
std_logic
;
SIGNAL
ipbus_rst
:
std_logic
;
-- ! IPBus reset to slaves
SIGNAL
ipbw
:
ipb_wbus_array
(
g_NUM_EXT_SLAVES
-1
DOWNTO
0
);
--! IBus write signals
...
...
@@ -453,7 +452,7 @@ BEGIN
)
PORT
MAP
(
clk_4x_logic_i
=>
clk_4x_logic
,
ipbus_clk_i
=>
ipbus_clk
_i
,
ipbus_clk_i
=>
ipbus_clk
,
logic_strobe_i
=>
strobe_4x_logic
,
logic_reset_i
=>
logic_reset
,
rst_fifo_i
=>
rst_fifo_o
,
...
...
@@ -470,8 +469,8 @@ BEGIN
edge_fall_i
=>
s_edge_falling
,
edge_rise_time_i
=>
s_edge_rise_times
,
edge_fall_time_i
=>
s_edge_fall_times
,
ipbus_i
=>
ipbw
(
9
),
ipbus_o
=>
ipbr
(
9
),
ipbus_i
=>
ipbw
(
6
),
ipbus_o
=>
ipbr
(
6
),
data_strobe_o
=>
data_strobe
,
event_data_o
=>
event_data
,
event_number_i
=>
event_number
,
...
...
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.cache.dat
View file @
cd30c695
No preview for this file type
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.xrf/top_extphy_struct.xrf
View file @
cd30c695
This diff is collapsed.
Click to expand it.
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd
View file @
cd30c695
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Click to expand it.
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/struct.bd.bak
View file @
cd30c695
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Click to expand it.
firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/top_extphy/symbol.sb
View file @
cd30c695
...
...
@@ -791,7 +791,7 @@ uid 1211,0
generic
(
GiElement
name
"g_NUM_EXT_SLAVES"
type
"positive"
value
"
10
"
value
"
7
"
e
"! Number of slaves outside IPBus interface"
)
uid
1213
,
0
...
...
@@ -1031,19 +1031,19 @@ value "/users/phdgc/IPBus_stuff/fmc_tlu_test_tpix3_nov14/fmc-mtlu/firmware/hdl_d
)
(
vvPair
variable
"date"
value
"1
1/28
/14"
value
"1
2/03
/14"
)
(
vvPair
variable
"day"
value
"
Fri
"
value
"
Wed
"
)
(
vvPair
variable
"day_long"
value
"
Fri
day"
value
"
Wednes
day"
)
(
vvPair
variable
"dd"
value
"
28
"
value
"
03
"
)
(
vvPair
variable
"entity_name"
...
...
@@ -1071,7 +1071,7 @@ value "phdgc"
)
(
vvPair
variable
"graphical_source_date"
value
"1
1/28
/14"
value
"1
2/03
/14"
)
(
vvPair
variable
"graphical_source_group"
...
...
@@ -1079,7 +1079,7 @@ value "users"
)
(
vvPair
variable
"graphical_source_time"
value
"1
6:43:34
"
value
"1
7:25:09
"
)
(
vvPair
variable
"group"
...
...
@@ -1119,7 +1119,7 @@ value "$HDS_PROJECT_DIR/fmc_mTLU_lib/ise"
)
(
vvPair
variable
"mm"
value
"1
1
"
value
"1
2
"
)
(
vvPair
variable
"module_name"
...
...
@@ -1127,11 +1127,11 @@ value "top_extphy"
)
(
vvPair
variable
"month"
value
"
Nov
"
value
"
Dec
"
)
(
vvPair
variable
"month_long"
value
"
Nov
ember"
value
"
Dec
ember"
)
(
vvPair
variable
"p"
...
...
@@ -1199,7 +1199,7 @@ value "symbol"
)
(
vvPair
variable
"time"
value
"1
6:52:05
"
value
"1
7:25:09
"
)
(
vvPair
variable
"unit"
...
...
@@ -2664,11 +2664,12 @@ st "Generic Declarations
g_NUM_DUTS positive 3
g_NUM_TRIG_INPUTS positive 4
g_NUM_EXT_SLAVES positive
10
--! Number of slaves outside IPBus interface
g_NUM_EXT_SLAVES positive
7
--! Number of slaves outside IPBus interface
g_EVENT_DATA_WIDTH positive 64
g_IPBUS_WIDTH positive 32
g_NUM_EDGE_INPUTS positive 4
g_SPILL_COUNTER_WIDTH positive 12 "
g_SPILL_COUNTER_WIDTH positive 12
"
)
header
"Generic Declarations"
showHdrWhenContentsEmpty
1
...
...
@@ -2687,7 +2688,7 @@ value "4"
(
GiElement
name
"g_NUM_EXT_SLAVES"
type
"positive"
value
"
10
"
value
"
7
"
e
"! Number of slaves outside IPBus interface"
)
(
GiElement
...
...
@@ -3378,7 +3379,7 @@ xt "42000,0,42000,0"
tm
"SyDeclarativeTextMgr"
)
)
lastUid
2
262
,
0
lastUid
2
308
,
0
okToSyncOnLoad
1
OkToSyncGenericsOnLoad
1
activeModelName
"Symbol:CDM"
...
...
firmware/scripts/aida_mini_tlu_addr_map.txt
View file @
cd30c695
...
...
@@ -3,7 +3,9 @@
FirmwareId 0x00000000 0xffffffff 1 0
* DUT interfaces base = 0x020
DUTMaskW 0x00000020 0xffffffff 0 1
DUTMaskR 0x00000021 0xffffffff 1 0
DUTIgnoreBusyW 0x00000021 0xffffffff 0 1
DUTMaskR 0x00000022 0xffffffff 1 0
DUTIgnoreBusyR 0x00000023 0xffffffff 1 0
*
* trigger inputs = 0x040
SerdesRstW 0x00000040 0xffffffff 0 1
...
...
firmware/scripts/test_aida_tlu_thresholds.py
View file @
cd30c695
...
...
@@ -36,4 +36,4 @@ boardi2c.set_dac(0,dacValue)
time
.
sleep
(
2.0
)
# set DACs to -5mV
boardi2c
.
set_threshold_voltage
(
7
,
-
0.0
0
5
)
boardi2c
.
set_threshold_voltage
(
7
,
-
0.05
)
firmware/scripts/test_aida_tlu_trig_counter.py
View file @
cd30c695
...
...
@@ -25,7 +25,7 @@ boardId = boardi2c.get_serial_number()
print
"FMC-TLU serial number = "
,
boardId
resetClocks
=
0
resetSerdes
=
1
resetSerdes
=
0
# set DACs to -200mV
print
"Setting all threshold DAC to -200mV "
...
...
@@ -47,10 +47,11 @@ if resetClocks:
#print "Clock status = " , hex(clockStatus)
inputStatus
=
board
.
read
(
"SerdesRst"
)
print
"Input status = "
,
hex
(
inputStatus
)
# Not all version of firmware have a serdes reset addres...
#inputStatus = board.read("SerdesRst")
#print "Input status = " , hex(inputStatus)
if
resetSerdes
:
if
resetSerdes
:
board
.
write
(
"SerdesRst"
,
0x00000003
)
inputStatus
=
board
.
read
(
"SerdesRst"
)
print
"Input status during reset = "
,
hex
(
inputStatus
)
...
...
@@ -73,8 +74,8 @@ numLoops = 5
for
iLoop
in
range
(
0
,
numLoops
):
inputStatus
=
board
.
read
(
"SerdesRst"
)
print
"Input status = "
,
hex
(
inputStatus
)
#
inputStatus = board.read("SerdesRst")
#
print "Input status = " , hex(inputStatus)
count0
=
board
.
read
(
"ThrCount0R"
)
print
" Count 0 = "
,
count0
...
...
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