@@ -41,7 +41,7 @@ Not all parameters are needed; if one of the parameters is not present in the fi
\item[CLOCK\_CFG\_FILE]\verb|[string, "./../user/eudet/misc/fmctlu_clock_config.txt"]| Name of the text file used to store the configuration values of the Si5345. The file can be generate using the Clockbuilder Pro software provided by \href{https://www.silabs.com/products/development-tools/software/clock}{SiLabs}.
\end{description}
\section{CONF file}
\section{CONF file}\label{ch:configFile}
\begin{description}
\item[confid]\verb|[string, "0"]| Does not serve any purpose in the code but can be useful to identify configuration settings used in a specific run. EUDAQ will store this information in the run data.
\item[verbose]\verb|[int, 0]| Defines the level of output messages from the \gls{tlu}. 0= only errors (minimum), 1= warning (default), 2= info, 3= all.
...
...
@@ -75,9 +75,13 @@ Not all parameters are needed; if one of the parameters is not present in the fi
\item[in1\_STR]\verb|[unsigned int, 0]| Same as \texttt{in1\_STR} but for input 1.
\item[in1\_DEL]\verb|[unsigned int, 0]| Same as \texttt{in1\_DEL} but for input 1.
\item[in2\_STR]\verb|[unsigned int, 0]| Same as \texttt{in1\_STR} but for input 2.
\item[in2\_DEL]\verb|[unsigned int, 0]| Same as \texttt{in1\_DEL} but for input 1.
\item[in2\_DEL]\verb|[unsigned int, 0]| Same as \texttt{in1\_DEL} but for input 2.
\item[in3\_STR]\verb|[unsigned int, 0]| Same as \texttt{in1\_STR} but for input 3.
\item[in3\_DEL]\verb|[unsigned int, 0]| Same as \texttt{in1\_DEL} but for input 1.
\item[in3\_DEL]\verb|[unsigned int, 0]| Same as \texttt{in1\_DEL} but for input 3.
\item[in4\_STR]\verb|[unsigned int, 0]| Same as \texttt{in1\_STR} but for input 4.
\item[in4\_DEL]\verb|[unsigned int, 0]| Same as \texttt{in1\_DEL} but for input 4.
\item[in5\_STR]\verb|[unsigned int, 0]| Same as \texttt{in1\_STR} but for input 5.
\item[in5\_DEL]\verb|[unsigned int, 0]| Same as \texttt{in1\_DEL} but for input 5.
\item[trigMaskHi]\verb|[unsigned int32, 0]| This word represents the most significative bits of the 64-bits used to determine the trigger mask.\\
A detailed explanation of how to determine the correct word is provided in section~\ref{ch:triggerLogic}.
\item[trigMaskLo]\verb|[unsigned int32, 0]| This word represents the least significative bits of the 64-bits used to determine the trigger mask.\\
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...
@@ -92,4 +96,10 @@ Not all parameters are needed; if one of the parameters is not present in the fi
\item[DUTIgnoreShutterVeto]\verb|[unsigned int, 0x1]| Set bit to 1 to tell the \gls{dut} to ignore the shutter signal.
\item[EnableRecordData]\verb|[boolean, true]| if set to 1, enable the data recording in the \gls{tlu}.
\item[InternalTriggerFreq]\verb|[unsigned int, 0]| Defines the rate of the trigger generated internally by the \gls{tlu}, in Hz: if 0, the internal triggers are disabled. Any other value activates the internal trigger generator with frequency equal to the parameter. Values above 160~MHz are coerced to 160~MHz.
\item[EnableShutterMode]\verb|[unsigned int, 0]| If set to 1, enables the use of the shutter mode described in section~\ref{ch:shutter}. Set to 0 to disable the shutter mode.
\item[ShutterSource]\verb|[unsigned int, 0]| Defines which of the six LEMO inputs is to be used to trigger the shutter sequence. The input should not be also used as part of the trigger validation.
\item[InternalShutterInterval]\verb|[unsigned int, 0]| Determines the period, in 25~ns clock cycles, of the internal shutter trigger. This can be used for debugging purposes. Set to 0 to disable this feature.
\item[ShutterOnTime]\verb|[unsigned int, 0]| Time between start of sequence and shutter asserted (t$_{1}$ in figure~\ref{fig:shutter_timing}). The value is defined in 25~ns clock units, i.e. a value of 3 corresponds to 75~ns.
\item[ShutterVetoOffTime]\verb|[unsigned int, 0]| Time between start of sequence and veto being de-asserted (t$_{2}$ in figure~\ref{fig:shutter_timing}). The value is defined in 25~ns clock units.
\item[ShutterOffTime]\verb|[unsigned int, 0]| Time between start of sequence and time at which shutter de-asserted and veto reasserted (t$_{3}$ in figure~\ref{fig:shutter_timing}). The value is defined in 25~ns clock units.
An optional ``shutter'' can be enabled. When the shutter is ``closed'' triggers are vetoed and no triggers are sent. When the shutter is ``open'' triggers can be generated and sent to active DUTs.
The shutter cycle can either be started by an external signal or synchronized by a counter clocked by the system clock.
The external signal, if used, must be connected to one of the trigger inputs. An appropriate threshold should be set and the input used for synchronizing the shutter should not be used in the trigger mask.
Figure \ref{fig:shutter_timing} illustrates the timing of the shutter. Behaviour of the shutter is controlled by the IPBus registers described in table \ref{tab:shutter_registers}.
\begin{table}
\begin{tabular}{lp{\0.6\linewidth}}
Register Name & Function \\\hline
ControlRW & Bit-0 controls if shutter pulses are active. (bit-0 = 1). Bit-1 selects external synchronization (bit-1 = 0) or internal sequence (bit-1 = 1) \\
ShutterSelectRW & Selects which input is used to trigger shutter sequence.()range = 0-5)\\
InternalShutterPeriodRW & Internal sequence period (when using internal sequence). Units of clock cycles.\\
ShutterOnTimeRW & Time between start of sequence and shutter asserted( t1) \\
ShutterVetoOffTimeRW & time between start of sequence and veto being de-asserted (t2)\\
ShutterOffTimeRW & Time between start of sequence and time at which shutter de-asserted and veto reasserted (t3) \\
\end{tabular}
\caption{IPBus registers controlling behaviour of shutter.}
\label{tab:shutter_registers}
\end{table}
An optional ``shutter'' can be enabled to synchronize the acquisition window to a signal, such as the spill signal from a beam line.\\
When the shutter is ``closed'' triggers are vetoed and no triggers are sent. When the shutter is ``open'' triggers can be generated and sent to active \gls{dut}s.\\
The shutter cycle can either be started by an external signal or synchronized by a counter clocked by the system clock (i.e. internally-generated shutter, which can be used to debug hardware).\\
The external signal, if used, must be connected to one of the six LEMO trigger inputs.\\
\begin{alertinfo}{If the external signal is used, an appropriate threshold should be set to the corresponding input. The input used for synchronizing the shutter should not be used in the trigger mask.}
\end{alertinfo}
Figure~\ref{fig:shutter_timing} illustrates the timing of the shutter sequence.\\
When the shutter is open, the \gls{tlu} will assert the \verb|CONT| line (see table~\ref{tab:HDMIpins}), indicating to the \gls{dut} that the sequence is active.\\
Behaviour of the shutter is controlled by the IPBus registers described in table~\ref{tab:shutter_registers}. If using EUDAQ, the registers can be written by including the corresponding steering parameters.
In this case, the easiest way to avoid potential conflict between the shutter signal and the trigger input is to connect the shutter input to LEMO 6 and then setting \verb|trigMaskHi= 0x0|. This means that the corresponding input is never involved in a valid active word. See section~\ref{ch:triggerLogic} for details.\\
The parameters should be included in the config file described in section~\ref{ch:configFile}.
\caption{Shutter Timing: the E$_{min}$ signal is fed to one of the trigger inputs and initiates the shutter sequence; after a programmable delay t$_{1}$ the \gls{tlu} asserts the \emph{shutter} signal. The unit will start to issue trigger signals to the \gls{dut} once a programmable time t$_{2}$ has elapsed. The window between t$_{1}$ and t$_{2}$ can be used to ensure the \gls{dut} is configured and ready to accept triggers. The unit will issue triggers until the end of the shutter window, determined by t$_{3}$.}
\label{fig:shutter_timing}
\end{figure}
%\begin{table}
% \begin{tabular}{lp{\0.6\linewidth}}
% Register Name & Function \\ \hline
% ControlRW & Bit-0 controls if shutter pulses are active. 1 = active. Bit-1 selects external synchronization (bit-1 = 0) or internal sequence (bit-1 = 1) \\
% ShutterSelectRW & Selects which input is used to trigger shutter sequence.range = 0-5)\\
% InternalShutterPeriodRW & Internal sequence period (when using internal sequence). Units of clock cycles.\\
% ShutterOnTimeRW & Time between start of sequence and shutter asserted( t1) \\
% ShutterVetoOffTimeRW & time between start of sequence and veto being de-asserted (t2)\\
% ShutterOffTimeRW & Time between start of sequence and time at which shutter de-asserted and veto reasserted(t3)\\
% \end{tabular}
% \caption{IPBus registers controlling behaviour of shutter.}
EnableShutterMode &\begin{tabular}[c]{@{}l@{}}If 1, shutter mode is enabled.\\ If 0, shutter mode is disabled.\end{tabular}&& ControlRW \\\hline
ShutterSource & Selects which input is used to trigger shutter sequence. & Range 0:5 & ShutterSelectRW \\\hline
InternalShutterInterval &\begin{tabular}[c]{@{}l@{}}Internal shutter period when using internal sequence.\\ Set to 0 to not use internal shutter generator.\end{tabular}&\begin{tabular}[c]{@{}l@{}}32-bit vale.\\ Units of 25 ns clock cycles.\end{tabular}& InternalShutterPeriodRW \\\hline
ShutterOnTime & Time between start of sequence and shutter asserted (t$_{1}$). &\begin{tabular}[c]{@{}l@{}}32-bit vale.\\ Units of 25 ns clock cycles.\end{tabular}& ShutterOnTimeRW \\\hline
ShutterVetoOffTime & Time between start of sequence and veto being de-asserted (t$_{2}$). &\begin{tabular}[c]{@{}l@{}}32-bit vale.\\ Units of 25 ns clock cycles.\end{tabular}& ShutterVetoOffTimeRW \\\hline
ShutterOffTime &\begin{tabular}[c]{@{}l@{}}Time between start of sequence and time at which\\ shutter de-asserted and veto reasserted (t$_{3}$).\end{tabular}&\begin{tabular}[c]{@{}l@{}}32-bit vale.\\ Units of 25 ns clock cycles.\end{tabular}& ShutterOffTimeRW \\\hline
\end{tabular}
\caption{Configuration parameters and corresponding IPBus registers controlling behaviour of shutter.}
@@ -17,8 +17,6 @@ The enable signals can be configured by programming two \gls{gpio} bus expanders
\begin{table}[]
\centering
\caption{HDMI pin connections.}
\label{tab:HDMIpins}
\begin{tabular}{|l|l|l|}
\hline
\textbf{HDMI PIN}&\textbf{HDMI Signal Name}&\textbf{Enable Signal Name}\\\hline
...
...
@@ -43,6 +41,8 @@ The enable signals can be configured by programming two \gls{gpio} bus expanders
18 & n.c. &\\\hline
19 & n.c. &\\\hline
\end{tabular}
\caption{HDMI pin connections.}
\label{tab:HDMIpins}
\end{table}
\begin{figure}
...
...
@@ -61,7 +61,7 @@ The enable signals can be configured by programming two \gls{gpio} bus expanders
In terms for functionalities, the four \gls{hdmi} connectors are identical with one exception: the clock signal from \verb|HDMI4| can be used as reference for the clock generator chip mounted on the hardware. For more details on this functionality refer to section~\ref{ch:clock}.
\subsubsection{SFP cage}
\brd hosts a \gls{sfp} cafe and a \gls{cdr} chip that can be used to decode a data stream over optical/copper interface. The data from the stream is routed to the \gls{fpga} while the clock can be fed to the Si5345 to provide a clock reference.
\brd hosts a \gls{sfp} cafe and a \gls{cdr} chip that can be used to decode a data stream or to issue timing signals over optical/copper interface. The data from the stream is routed to the \gls{fpga} while the clock can be fed to the on-board clock chip to be used as a clock reference.
\section{Clock LEMO}
The board hosts a two-pin LEMO connector that can be used to provide a reference clock to the clock generator (see section~\ref{ch:clock}) or to output the clock from the \gls{tlu} to the external world, for instance to use it as a reference for another \gls{tlu}. The signal level is 3.3~V \gls{lvds}.\\
Congratulations on acquiring an AIDA2020 \gls{tlu}. We hope that the unit will help you to collect lots of useful data during your hardware tests.\\
Congratulations on acquiring an AIDA2020 \gls{tlu}!\\
We hope that the unit will help you to collect lots of useful data during your hardware tests.\\
This manual describes the \gls{tlu} designed for the \href{http://aida2020.web.cern.ch/}{AIDA-2020 project} by David Cussans\footnote{University of Bristol, Particle Physics group} and Paolo Baesso\footnote{University of Bristol, Particle Physics group}.\\
The unit is designed to be used in High Energy Physics beam-tests and provides a simple and flexible interface for fast timing and triggering signals at the AIDA pixel sensor beam-telescope.\\
The current version of the hardware is an evolution of the \href{https://twiki.cern.ch/twiki/bin/view/MimosaTelescope/TLU}{EUDET-TLU} and the \href{https://www.ohwr.org/projects/fmc-mtlu/wiki}{miniTLU} and is shipped in a metal enclosure that includes an \gls{fpga} board, the \gls{tlu}\gls{pcb} and an additional power module: the \gls{fpga} is responsible for all the logic functions of the unit, while the \gls{pcb} contains the clock chip, discriminator and interface blocks needed to communicate with other devices. The power module contains programmable \gls{dac} to power photomultipliers and \gls{led} indicators.\\
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@@ -10,19 +11,19 @@ The AIDA \gls{tlu} provides timing and synchronization signals to test-beam read
When used for within AIDA-2020 specifications, the hardware generates a low-jitter 40~MHz clock or can accept an external clock reference. The external reference clock frequency is not required to be 40~MHz but other values require a dedicated configuration of the clock circuitry on the board. Similarly, by changing the configuration file it is possible to operate the hardware at different clock frequencies.\\
The \gls{tlu} accepts asynchronous trigger signals from up to six external sources, such as beam-scintillators, and generate synchronous signals (including global trigger or control signals) to send to up to four \gls{dut}. The logic function used to generate the trigger can be defined by the user among all the possible logic combinations of the inputs.\\
Depending on the chosen mode of operation, the \gls{tlu} can accept busy signals or other veto signals from \gls{dut}s and react accordingly, for instance avoiding any further trigger until all the busy signals have been de-asserted.\\
Whenever a global trigger is generated by the unit, a 48-bit coarse time-stamp is attached to it. This time stamp is based on the internal clock. The unit also records a fine-grain time stamp with 780~ps resolution for each signal involved in the trigger decision.\\
Whenever a global trigger is generated by the unit, a 48-bit coarse time-stamp is attached to it. This time stamp is based on the internal 40~MHz clock. The unit also records a fine-grain time stamp with 1.56~ns resolution for each signal involved in the trigger decision.\\
The configuration parameters and data are sent and received via the \href{https://www.ohwr.org/projects/ipbus}{IPbus} which provides a simple way to control and communicate TCA-based hardware via the UDP/IP protocol.\\
The \gls{tlu} is shipped with an \gls{fpga} board already programmed with the latest version of the firmware needed to operate the unit. New features and bug fixes are continuously being implemented by the developing team and it is possible to flash the unit with a new firmware as described in section~\ref{ch:flashFPGA}.\\
The unit requires 12~V to operate. Power can be provided using the circular socket located on the back panel. See section~\ref{ch:backpanelintro} for details on compatible connectors.\\
During normal operation the current drawn by the unit is about 1~A.\\
The internal electronics of the \gls{tlu} require 12~V to operate and will dissipate about 12 W during normal operation.\\
Power should be provided using the socket located on the back panel. See section~\ref{ch:backpanelintro} and \ref{ch:rackmountpanel} for details on compatible connectors.\\
The unit is provided in two different configurations: a table-top enclosure and a 19"-rack mount enclosure. The difference is only cosmetic; the hardware inside the unit is identical\footnote{With the only exception that the 10"-rack unit has and additional \gls{lcd}.} so the information contained in the rest of this manual apply to both types of \gls{tlu} unless otherwise specified.
The unit is provided in two different configurations: a table-top enclosure (figure~\ref{fig:tabletop}) and a 19"-rack mount enclosure (figure~\ref{fig:rackmountpanels}). The difference is only cosmetic; the hardware inside the unit is identical\footnote{With the only exception that the 19"-rack unit has and additional \gls{lcd} and is powered using 220~V.} so the information contained in the rest of this document apply to both types of \gls{tlu} unless otherwise specified.
\subsection{Table-top unit: front panel}\label{ch:frontpanel}
The front panel of the \gls{tlu} is shown in figure~\ref{fig:tabletop} (top); from left to right, the main elements are:
\begin{itemize}
\item\gls{sfp} cage
\item\gls{sfp} cage. This port can be used to provide timing signals via optical/copper interface. Do not attempt to use this to communicate with the \gls{tlu} as the firmware does not support this mode of operation.
\item 4 \gls{hdmi} connectors for devices under test. Each connector has a \gls{rgb} LED used to indicate the port status (see section~\ref{ch:frontpanelintro}).
\item 1 LEMO connector for \gls{lvds} clock input/output. This is a 2-pin LEMO series 00 connector\footnote{Part number EPG.00.302.NLN. An example of mating part is LEMO FGG.00.302.CLAD35}. A \gls{rgb}\gls{led} indicator is used to signal whether the port is configured as input or output.
\item 6 LEMO Trigger inputs. These are standard 1-pin LEMO connectors\footnote{LEMO EPK.00.250.NN. Mates with any LEMO 00.250 connector}. Each input has a \gls{rgb}\gls{led} indicator.
...
...
@@ -31,7 +32,7 @@ The front panel of the \gls{tlu} is shown in figure~\ref{fig:tabletop} (top); fr
To reduce the cost of a unit, some modules are not equipped with these connectors and the front panel holes are blanked by a plastic board.\\
If necessary, it is possible to solder the connectors at a later stage, since all the necessary circuitry is present. This requires disassembling the unit, removing the top cover. See section~\ref{ch:inspection} for details.
\end{alertinfo}
\item Green \gls{led} indicators for power (+12 V) and regulators (+5 V and -5 V).
\item Green \gls{led} indicators for power (+12 V) and regulators (+5 V and -5 V). These indicators should always be lit when the unit is powered.
\end{itemize}
\begin{figure}
\centering
...
...
@@ -57,14 +58,14 @@ A cooling fan is also mounted on the back panel.
The front and back panels for the 19"-rack unit are shown in figure~\ref{fig:rackmountpanels}. All the components are identical to those of the table-top enclosure with the following exceptions:
\begin{itemize}
\item this version has a \gls{lcd} used to display information.
\item the unit is powered with 220~V (AC) instead of 12~V (DC). A standard mains lead\footnote{IEC 60320 type C13.} is required.
\item the unit is powered with 220~VAC (110 VAC can also be used); an internal AC-DC converter is used to provide the required 12~V (DC) to the electronics. A standard mains lead\footnote{IEC 60320 type C13.} is required.
\item The \gls{usb} ports are placed on the front of the unit leaving only the RJ45 and power connectors on the back.
\item A power switch is located on the front panel.
\caption{View of the 10"-rack mount TLU front (top) and back (bottom) panels.}
\caption{View of the 19"-rack mount TLU front (top) and back (bottom) panels.}
\label{fig:rackmountpanels}
\end{figure}
...
...
@@ -73,27 +74,27 @@ The front and back panels for the 19"-rack unit are shown in figure~\ref{fig:rac
At the moment of shipping, each \gls{tlu} is pre-configured with the most recent version of the firmware. It is therefore possible to power the unit and start using it almost immediately. The following steps are required to use the unit:
\begin{enumerate}
\item Ensure no \gls{usb} cable is plugged in the unit
\item Power the unit using the provided power supply (+12~V) or an equivalent power supply. The pre-configured firmware will automatically load.
\item Plug an Ethernet cable in the back panel and connect it to the computer used to run the control software. Note that currently the unit uses a pre-defined IP address of 192.168.200.30. In future version of the firmware the address will be configurable.
\item Power the unit. The pre-configured firmware will automatically load.
\item Plug an Ethernet cable in the RJ45 socket located on the back panel and connect it to the computer used to run the control software. Note that currently the unit uses a pre-defined IP address of 192.168.200.30. In future version of the firmware the address will be configurable. Try to ping the IP address of the unit: if the unit responds then the firmware is correctly loaded.
\item Use the control software to configure the unit. In particular, after each power up it is necessary to re-configure the clock chip. See chapter~\ref{ch:controlsw} for details on the software and chapter~\ref{ch:clock} for details on the clock chip.
\end{enumerate}
\section{FPGA and firmware}\label{ch:fpgahardware}
The firmware developed at University of Bristol is targeted to work with the Enclustra AX3 board, which must be plugged onto a PM3 base, also produced by \href{http://www.enclustra.com/en/home/}{Enclustra}. The firmware is written on the \gls{fpga} using a \gls{jtag} interface. Typically a breakout board will be required to connect the Xilinx programming cable to the Enclustra PM3. All these components are included in the \gls{tlu} enclosure so the user can upload a new version of the firmware by simply connecting a \gls{usb}-B cable in the back panel of the unit.\\
At the time of writing this work\footnote{\monthyeardate\today} the AX3 is the only \gls{fpga} for which a firmware has been developed. However, we plan to ship future versions of the \gls{tlu} with a custom made \gls{fpga} designed by Samer Kilani.\\
The firmware developed at University of Bristol is targeted to work with the Enclustra AX3 board, which must be plugged onto a PM3 base, also produced by \href{http://www.enclustra.com/en/home/}{Enclustra}. The firmware is loaded on the \gls{fpga} using a \gls{jtag} interface. Typically a breakout board will be required to connect the Xilinx programming cable to the Enclustra PM3. All these components are included in the \gls{tlu} enclosure so the user can upload a new version of the firmware by simply connecting a \gls{usb}-B cable in the back panel of the unit.\\
At the time of writing this document\footnote{\monthyeardate\today} the AX3 is the only \gls{fpga} for which a firmware has been developed.\\
Each unit is shipped with the latest version of the firmware written onto its boot loader \gls{eeprom}; at power up, the unit will automatically retrieve the firmware from the \gls{eeprom} and program itself.
\begin{alertinfo}{Note}
If the \gls{fpga} detects a programming cable connected it will not load the firmware from its memory after a power cycle.\\
It is recommended to leave the \gls{usb} cable disconnected from the back panel unless there is the intention to re-program the firmware.
\end{alertinfo}
The latest version of the firmware can be found on the project \gls{ohwr} github repository (\href{https://ohwr.org/project/fmc-mtlu-gw}{AIDA-2020 TLU - Gateware}).\\
The user can decide to configure the unit with a new version of the firmware that will remain active until the \gls{tlu} is powered off (standard programming). It is also possible to write the \gls{eeprom} to replace boot program with a new one (configuration memory programming). Both procedures are described below.\\
The user can decide to configure the unit with a new version of the firmware that will remain active until the \gls{tlu} is powered off (see \hyperlink{standard programming}{standard programming}, described below). It is also possible to re-program the \gls{eeprom} to permanently replace the boot program with a new one (see \hyperlink{configuration memory programming}{configuration memory programming}, described below).\\
Programming the \gls{fpga} requires the Vivado Lab Tools, available free on the \href{https://www.xilinx.com/support/download.html}{on the Xilinx website}\footnote{https://www.xilinx.com/support/download.html}. Depending on the hardware installed internally, some additional drivers might be required to correctly use the \gls{jtag} cable.\\
At the time of writing, the preferred cable for the table-top \gls{tlu} is the \href{https://store.digilentinc.com/jtag-hs2-programming-cable/}{Digilent HS2}\footnote{https://store.digilentinc.com/jtag-hs2-programming-cable/}; the corresponding driver package is ADEPT 2, available on the \href{https://reference.digilentinc.com/reference/software/adept/start}{Digilent website}\footnote{https://reference.digilentinc.com/reference/software/adept/start}.\\
For the 19-inch rack mount unit, the cable used is the Trenz \href{https://shop.trenz-electronic.de/en/TE0790-02-XMOD-FTDI-JTAG-Adapter-Xilinx-compatible?c=318}{TE0790-02}\footnote{https://shop.trenz-electronic.de/en/TE0790-02-XMOD-FTDI-JTAG-Adapter-Xilinx-compatible?c=318}. This cable is compatible with Xilinx products and does not require additional software.
Updating the firmware on the \gls{tlu} requires writing a bit stream file to its \gls{fpga}.
\hypertarget{standard programming}{Updating} the firmware on the \gls{tlu} requires writing a bit stream file to its \gls{fpga}.
This operation is performed using the left \gls{usb} port located on the back panel, labelled \verb"FPGA PROGRAMMING" in figure~\ref{ch:backpanelintro}.\\
Once the Vivado tools have been installed the user should also install the drivers for the programming cable in the enclosure (see previous section for software sources).\\
The bit stream is provided as a \verb".bit" file and can be found on the firmware \href{https://ohwr.org/project/fmc-mtlu-gw}{\gls{ohwr} repository} for the \gls{tlu}\footnote{https://ohwr.org/project/fmc-mtlu-gw/tree/master/AIDA\_tlu/bitFiles}.\\
...
...
@@ -117,8 +118,8 @@ Once these prerequisites are met, the procedure is as follows:
The procedure to write a permanent program in the \gls{eeprom} is very similar to the one followed to write a bit stream file, with the exception that the user should select \verb"Add configuration memory device" in the options, as shown in figure~\ref{fig:hw_addMemory}.
\hypertarget{configuration memory programming}{The procedure} to write a permanent program in the \gls{eeprom} is very similar to the one followed to write a bit stream file, with the exception that the user should select \verb"Add configuration memory device" in the options, as shown in figure~\ref{fig:hw_addMemory}.
This will open a new window, shown in figure~\ref{fig:hw_eeprom}, from which it is possible to indicate the file to use (with extension \verb".mcr").
\begin{figure}
\centering
...
...
@@ -130,7 +131,7 @@ Make sure that the options are set as shown in figure~\ref{fig:hw_eeprom}.\\
The firmware loaded this way will overwrite any pre-existing firmware and will be loaded automatically whenever the unit is powered up.
\section{Inspection (table top unit)}\label{ch:inspection}
At some point someone, somewhere, will want to disassemble the unit to poke at its internal electronics; the top cover of the unit can only slide away when either the front or back frame are removed.
The top cover of the unit can only slide away when either the front or back frame are removed.
\begin{alertinfo}{Note}
Simply removing the corner screws on the panels will only allow to remove the plates but not accessing the inside of the unit.
\end{alertinfo}
...
...
@@ -144,18 +145,18 @@ F) Slide the top cover away.\\
The same procedure can be repeated with the front frame, if necessary. In this case, the user must also disconnect the front panel from the electronics by removing the countersunk screws connected to the \gls{hdmi} ports and the powermodule.
\caption{Steps to remove the cover from the unit. The screws to take the unit apart are hidden behind the corner plates. The plates can be removed by pulling.}
\label{fig:dismantle}
\end{figure}
\section{Inspection (19"-rack unit)}
Accessing the hardware on the 19"-unit is more straightforward: simply remove the four M2.5 Pozi screws located on the top panel and slide the panel away. Please note that this unit has an internal AC-DC converter that can potentially store an harmful amount of energy even when powered-off and disconnected from the mains: always use care when accessing the unit.
Accessing the hardware on the 19"-unit is straightforward: simply remove the four M2.5 screws located on the top panel and slide the panel back. Please note that this unit has an internal AC-DC converter that can potentially store an harmful amount of energy even when powered-off and disconnected from the mains: always use care when accessing the unit.
\begin{alertinfo}{Danger}
Before disassembling the 19-inch rack mounted \gls{tlu} disconnect the mains cable from the back and leave sufficient time for the internal capacitors to discharge.
The \gls{tlu} can use various sources to produce a stable 40~MHz clock\footnote{For some applications a 50~MHz clock will be required instead}. A \gls{lvpecl} crystal provides the reference 50~MHz clock for a Si5345A jitter attenuator. The Si5345A can accept up to four clock sources and use them to generate the required output clocks.\\
The \gls{tlu} can use various sources to produce a stable 40~MHz clock\footnote{For some applications a 50~MHz clock will be required instead}.\\
A \gls{lvpecl} crystal provides the reference 50~MHz clock for a Si5345A jitter attenuator. The Si5345A can accept up to four clock sources and use them to generate the required output clocks.\\
In \brd the possible sources are: differential LEMO connector LM1\_9, one of the four \gls{hdmi} connectors (\verb|HDMI4|), a \gls{cdr} chip connected to the \gls{sfp} cage. The fourht input is used to provide a zero-delay feedback loop.\\
The low-jitter clock generated by the Si5345A can be distributed to up to ten recipients. In the \gls{tlu} these are: the four \gls{dut}s via \gls{hdmi} connectors, the differential LEMO cable, the \gls{fpga}, connector J1 as a differential pair (pins 4 and 6) and as a single ended signal (pin 8). The final output is connected to the zero-delay feedback loop. Note that it is possible to program the clock chip to generate a different frequency for each of its outputs.\\
The \gls{dut}s can receive the clock either from the Si5435A or directly from the \gls{fpga}: when provided by the clock generator, the signal name is \verb|CLK\_TO\_DUT| and is enabled by signal \verb|ENABLE_CLK_TO_DUT|; when the signal is provided directly from the \gls{fpga} the line used is \verb|DUT_CLK_FROM_FPGA| and is enabled by \verb|ENABLE_DUT_CLK_FROM_FPGA|.\\
@@ -4,6 +4,8 @@ This repository is only used to provide the most up-to-date documentation for th
The documentation is provided as a LaTex project. The file [Main_TLU.pdf](./Documentation/Main_TLU.pdf) is a compiled PDF version of the documentation.
For a quick guide on how to setup and start using the TLU, see the manual section **Setup**.
## How to access the TLU software, hardware and firmware files
The **CAD** design files for the TLU can be accessed via a dedicated hardware repository (**https://ohwr.org/project/fmc-mtlu-hw/**).
