... | @@ -47,32 +47,26 @@ differentiates the board executions. |
... | @@ -47,32 +47,26 @@ differentiates the board executions. |
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|**Form-factor**|FMC, LPC connector|
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|**Form-factor**|FMC, LPC connector|
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|**WorldFIP connector**|Micro Sub-D 9 pins|
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|**WorldFIP connector**|Micro Sub-D 9 pins|
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|**WorldFIP interface**|[FielDrive](https://www.ohwr.org/project/cern-fip/wikis/FielDrive) + [FieldTR](https://www.ohwr.org/project/cern-fip/wikis/FieldTR) (Alstom)|
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|**WorldFIP interface**|[FielDrive](https://www.ohwr.org/project/cern-fip/wikis/FielDrive) + [FieldTR](https://www.ohwr.org/project/cern-fip/wikis/FieldTR) (Alstom)|
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|**Bus speed**|31.25k, 1M, 2.5M, 5M (different executions of hardware)
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|**Bus speed**|31.25k, 1M, 2.5M, 5M (different executions of hardware)<br>Note that the 5M version is supported by the hw but is has not been tested and is not supported by the current gw/sw/lib|
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Note that the 5M version is supported by the hw but is has not been tested and is not supported by the current gw/sw/lib|
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|**External sync. input**|Optional sync of the WorldFIP start of macrocycle; LEMO 0 connector; TTL; Software selectable 50 Ohms termination|
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|**External sync. input**|Optional sync of the WorldFIP start of macrocycle; LEMO 0 connector; TTL; Software selectable 50 Ohms termination|
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|**Front panel LEDs**|FMC TX ACT : at the end of a macrocycle there has been no transmission failure
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FMC TX ERR: at the end of a macrocycle transmission errors have been detected
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FMC RX ACT: at the end of a macrocycle there has been no reception failure
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FMC RX ERR: at the end of a macrocycle reception errors have been detected
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FMC SYNC ACT: application expects sync pulse and it is receiving it successfully
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FMC SYNC ERR: application expects sync pulse which it is not arriving
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SPEC GREEN: blinking using the 100 MHz clock
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SPEC RED: PCIe reset|
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|**Test points**|Four through hole test points (TP) next to the FMC connector
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TP1: connected to FielDrive RXD
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TP2: connected to FielDrive TXD
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TP3: connected to Mock Turtle led&dbg reg bit 8
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TP4: connected to Mock Turtle led&dbg reg bit 9|
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|**Power Consumption**|200 mA|
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|**Power Consumption**|200 mA|
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|**Front panel LEDs**|**FMC TX ACT**: at the end of a macrocycle there has been no transmission failure<br>**FMC TX ERR**: at the end of a macrocycle transmission errors have been detected<br>**FMC RX ACT:** at the end of a macrocycle there has been no reception failure<br>**FMC RX ERR**: at the end of a macrocycle reception errors have been detected<br>**FMC SYNC ACT**: application expects sync pulse and it is receiving it successfully<br>**FMC SYNC ERR**: application expects sync pulse which it is not arriving<br>**SPEC GREEN**: blinking using the 100 MHz clock<br>**SPEC RED**: PCIe reset|
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|**Test points**|Four through hole test points (TP) next to the FMC connector:<br>**TP1:** connected to FielDrive RXD<br>**TP2:** connected to FielDrive TXD<br>**TP3:** connected to Mock Turtle led&dbg reg bit 8<br>**TP4:** connected to Mock Turtle led&dbg reg bit 9|
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-----
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-----
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## Project information
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## Project information
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- **Official production documentation (schematics, PCB, etc.):**
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- [Design Guide](https://www.ohwr.org/project/masterfip/wikis/Documents/Design-Guide)
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[EDMS: EDA-03098](https://edms.cern.ch/project/EDA-03098)
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- [Board EMC Tests](https://www.ohwr.org/project/fmc-masterfip/wikis/Documents/board-(V1)-EMC-tests)
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- Currently supported versions:
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- [Board Consumption & Temperature
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Tests](https://www.ohwr.org/project/fmc-masterfip/wikis/Documents/board-(V1)-temperature-&-consumption)
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- [Frequently Asked Questions](FAQ)
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- Official production documentation (schematics, PCB, etc.):
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[EDMS: EDA-03098](https://edms.cern.ch/project/EDA-03098) <br>
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Currently supported versions:
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- FmcWorldFIP V4 - Bus speed **31.25k** -
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- FmcWorldFIP V4 - Bus speed **31.25k** -
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[EDA-03098-V4-0](https://edms.cern.ch/item/EDA-03098-V4-0)
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[EDA-03098-V4-0](https://edms.cern.ch/item/EDA-03098-V4-0)
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- FmcWorldFIP V4 - Bus speed **1M** -
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- FmcWorldFIP V4 - Bus speed **1M** -
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... | @@ -80,22 +74,13 @@ TP4: connected to Mock Turtle led&dbg reg bit 9| |
... | @@ -80,22 +74,13 @@ TP4: connected to Mock Turtle led&dbg reg bit 9| |
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- FmcWorldFIP V4 - Bus speed **2.5M** -
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- FmcWorldFIP V4 - Bus speed **2.5M** -
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[EDA-03098-V4-2](https://edms.cern.ch/item/EDA-03098-V4-2)
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[EDA-03098-V4-2](https://edms.cern.ch/item/EDA-03098-V4-2)
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\> | **Version**| **Schematics**| **Comments**|
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|**Version**|**Schematics**|**Comments**|
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\> |**V1**| EDA-03098-V1-0, EDA-03098-V1-1, EDA-03098-V1-2,
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|----|----|----|
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EDA-03098-V1-3| First version|
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|**V1**|EDA-03098-V1 -0/1/2/3| First version|
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\> |**V2**| EDA-03098-V2-0, EDA-03098-V2-1, EDA-03098-V2-2,
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|**V2**|EDA-03098-V2 -0/1/2/3| Corrections on V1|
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EDA-03098-V2-3| Corrections on V1|
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|**V3**|EDA-03098-V3 -0/1/2/3| V2 simplified, without ADC|
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\> |**V3**| EDA-03098-V3-0, EDA-03098-V3-1, EDA-03098-V3-2,
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|**V4**|EDA-03098-V4 -0/1/2/3|V3 with small modification on the placement of front panel LEDs|
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EDA-03098-V3-3| V2 simplified, without ADC|
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\> |**V4**| EDA-03098-V4-0, EDA-03098-V4-1, EDA-03098-V4-2,
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EDA-03098-V4-3| V3 with small modification on the placement of front
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panel LEDs|
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- [Design Guide](https://www.ohwr.org/project/masterfip/wikis/Documents/Design-Guide)
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- [Board EMC Tests](https://www.ohwr.org/project/fmc-masterfip/wikis/Documents/board-(V1)-EMC-tests)
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- [Board Consumption & Temperature
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Tests](https://www.ohwr.org/project/fmc-masterfip/wikis/Documents/board-(V1)-temperature-&-consumption)
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- [Frequently Asked Questions](FAQ)
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-----
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-----
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... | @@ -129,12 +114,11 @@ designer - CERN |
... | @@ -129,12 +114,11 @@ designer - CERN |
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|28-03-2017|15 V3 prototype cards received; validated and they are ok!|
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|28-03-2017|15 V3 prototype cards received; validated and they are ok!|
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|17-07-2017|Long runs of V3 boards in the lab and in CHARM|
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|17-07-2017|Long runs of V3 boards in the lab and in CHARM|
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|06-09-2017|Production of 130 v4 masterFIP boards started, to be available by early December 2017|
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|06-09-2017|Production of 130 v4 masterFIP boards started, to be available by early December 2017|
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|15-02-2018|Installation of 50 boards in the LHC for Power Converters; design validated|
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|16-05-2018|Reception of 100 v4 masterFIP boards for TS1 installations|
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|16-05-2018|Reception of 100 v4 masterFIP boards for TS1 installations|
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|15-06-2018|Installation of 30 more boards in the LHC for Power Converters|
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|13-07-2018|Reception of 500 v4 masterFIP boards|
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|13-07-2018|Reception of 500 v4 masterFIP boards|
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|15-02-2020|500 boards being installed in the LHC for different equipment groups like Power-Converters, Quench-Protection, Cryogenics|
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-----
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*Matthieu Cattin, Eva Gousiou, Erik van der Bij, 3 September 2018*
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